ISL6261EVAL1Z Intersil, ISL6261EVAL1Z Datasheet - Page 20

• Manufacturer Part Number: ISL6261EVAL1Z
• Description: EVAL BOARD FOR ISL6261 1 QFN
• Manufacturer: Intersil

Specifications of ISL6261EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

R
droop amplifier gain, according to Equation 22:
After determining R
calculate the droop resistances R
R
The effectiveness of the R
coupling coefficient between the NTC thermistor and the
inductor. The NTC thermistor should be placed in close
proximity of the inductor.
To verify whether the NTC network successfully compensates
the DCR change over temperature, one can apply full load
current, and wait for the thermal steady state, and see how
much the output voltage deviates from the initial voltage
reading. Good thermal compensation can limit the drift to less
than 2mV. If the output voltage decreases when the
temperature increases, that ratio between the NTC thermistor
value and the rest of the resistor divider network has to be
increased. Following the evaluation board value and layout of
NTC placement will minimize the engineering time.
The current sensing traces should be routed directly to the
inductor pads for accurate DCR voltage drop measurement.
However, due to layout imperfection, the calculated R
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust R
has achieved thermal equilibrium at full load. For example, if
the max current is 20A, one should apply 20A load current
and look for 42mV output voltage droop. If the voltage droop
is 40mV, the new value of R
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. The
effective resistance on the VSUM pin is the parallel of R
R
of R
Dynamic Mode of Operation – Droop Capacitor
Design in DCR Sensing
Figure 10 shows the desired waveforms during load
transient response. V
at I
factors, namely the choice of output inductor and output
capacitor, the compensator design, and the droop capacitor
design.
k
R
R
drp1
droop
n
droopamp
drp
, and the effective resistance on the DFB pin is the parallel
drp
core
drp1
2
(R
2
=
is 2.1mV/A per lntel
_
change. The V
11
new
and R
(
=
DCR
in Figure 2) and R
1
=
+
drp2
R
R
⋅
R
42
40
G
drp
droop
drp
.
( 1
s
mV
mV
2
1
25
and R
core
core
o
C
needs to be as square as possible
(
response is determined by several
n
®
)
R
n
network is sensitive to the
dpr2
−
IMVP-6
networks, use Equation 23 to
20
drp2
drp
) 1
1
is calculated by:
⋅
(R
drp1
R
+
12
drp
®
R
drp2
and R
1
specification.
in Figure 2) sets the
drp
after the system
2
)
drp2
−
.
R
drp
1
(EQ. 22)
(EQ. 23)
(EQ. 24)
drp2
s
and
ISL6261
The droop capacitor refers to C
designed correctly, its voltage will be a high-bandwidth
analog voltage of the inductor current. If C
correctly, its voltage will be distorted from the actual
waveform of the inductor current and worsen the transient
response. Figure 11 shows the transient response when C
is too small. V
application to create a system failure. Figure 12 shows the
transient response when C
drooping to its final value. There will be excessive overshoot
if a load occurs during this time, which may potentially hurt
the CPU reliability.
The current sensing network consists of R
effective resistance is the parallel of R
constant of the current sensing network needs to match the
L/DCR time constant of the inductor to get correct
representation of the inductor current waveform. Equation 25
shows this equation:
DCR
FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN C
FIGURE 11. LOAD TRANSIENT RESPONSE WHEN C
L
=
V
V
V
⎛
⎜ ⎜
⎝
core
core
core
R
R
WAVEFORMS
SMALL
LARGE
n
n
core
×
+
Δ
R
R
may sag excessively upon load
V
s
s
core
⎞
× ⎟ ⎟
⎠
=
C
V
V
V
i
i
i
core
core
core
n
n
Δ
core
core
core
is too large. V
I
core
n
in Figure 9. If C
×
R
droop
n
and R
Δ
Δ
V
n
n
I
core
, R
core
core
is not designed
s
s
. The RC time
September 27, 2006
is sluggish in
and C
n
is
n
n
(EQ. 25)
IS TOO
IS TOO
n
FN9251.1
. The
n