MPC8572EAMC Freescale Semiconductor, MPC8572EAMC Datasheet - Page 53

• Manufacturer Part Number: MPC8572EAMC
• Description: MPC8572 AMC RAPID SYSTEM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8572EAMC

• Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MPC8572E

To examine the debug information from the MMC the UART output from the MCF5213 is connected via
an RS-232 transceiver to the 3-way header, J2.
header.
To assist with CPLD debug and system bring-up a specific header is used to include or isolate the System
CPLD from the AdvancedMC JTAG chain.
5.4.2
The Reset CPLD is a critical component on the MPC8572EAMC design. This device is responsible for
providing the following functions:
The Reset CPLD is based around the Altera EPM240T100C5N device. The internal operation of this Reset
CPLD is factory programmed and is reserved for factory use only.
The Altera MaxII EPM1270 System CPLD is responsible for reset, POR configuration of the MPC8572E,
signal fan-out, logic/pin multiplexing, COP/JTAG control (of the CPLD itself, the AdvancedMC JTAG
and MPC8572E JTAG signals). One of the main methods by which a user can configure the board is
through the use of three on-board DIP switches. These switches are read by the System CPLD during the
MPC8572E’s POR configuration cycle phase. The function of these DIP switches is detailed in the tables
below. The following table syntax is used:
Freescale Semiconductor
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Generating a board reset signal
Synchronizing all CPLD signals to the input CPLD clock
Checking the presence of a 12-V power supply
Powering up all board power supplies (in the correct sequence)
Bringing up all devices out of reset (in the correct sequence)
Giving the System CPLD a “go” to start the POR Config cycles
Board CPLD Logic/POR Configuration
“1” implies a logic high. This is achieved by turning the switch off.
“0” implies a logic low. This is achieved by turning the switch on.
Pin #
MPC8572EAMC Advanced Mezzanine Card User Guide, Rev. 1.2
1
2
3
Pin #
1
2
3
CPLD_TDO
RESET_TDO
SYSTEM_TDO
Table 5-20. J2—MCF5213 Serial Interface
Table 5-21. J12—CPLD Debug Interface
TXD
RXD
GND
Signal
Signal
Serial Receive Data input
Serial Transmit Data output
Digital ground
Table 5-21
Table 5-20
JTAG TDO from CPLD
JTAG TDO from Reset CPLD
JTAG TDO from System CPLD
Description
illustrates the pin connections of this interface.
shows the different pin connections of this
Description
MPC8572EAMC Functional Description
5-29