DC1398A-GA Linear Technology, DC1398A-GA Datasheet - Page 8

• Manufacturer Part Number: DC1398A-GA
• Description: BOARD EVAL LTM9001-GA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1398A-GA

• Design Resources: Demo Circuit 1398A Schematic
• Frequency: 0Hz ~ 300MHz
• Kit Contents: Board, Manual
• Features: LTM9001 16bit Receiver Subsystem, DC-10MHz LPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Development Tool Type: Hardware - Eval/Demo Board
• Mcu Supported Families: LTM9001
• For Use With/related Products: LTM9001
• Lead Free Status / RoHS Status: Not applicable / Not applicable

LTM9001-GA
PIN FUNCTIONS
Supply Pins
V
The voltage on this pin provides power for the amplifi er
stage only and is internally bypassed to GND.
V
supply is internally bypassed to GND.
OV
Drivers. This supply is internally bypassed to OGND.
GND (Pins A1, A2, A4, B2, B4, C2, C4, D1, D2, D4, E4, F1,
F2, F4, G2, G4, H2, H4, J1, J2, J4): Analog Ground.
OGND (Pins A5, A9, G8, J9): ADC Output Driver Ground.
Analog Inputs
IN
IN
DNC (Pins C3, D3): Do Not Connect. These pins are used
for testing and should not be connected on the PCB. They
may be soldered to unconnected pads and should be well
isolated. The DNC pins connect to the signal path prior to
the ADC inputs; therefore, care should be taken to keep
other signals away from these sensitive nodes.
NC (See Pin Confi guration Table for Pin Locations): No
Connect.
CLK (Pin B1): Clock Input. The sampled analog input is
held on the falling edge of CLK. The output data may be
latched on the rising edge of CLK.
Control Inputs
SENSE (Pin J3): Reference Mode Select and External
Reference Input. Tie SENSE to V
2.5V bandgap reference. An external reference of 2.5V
or 1.25V may be used; both reference values will set the
maximum full-scale input range.
AMPSHDN (Pin H3): Power Shutdown Pin for Amplifi er.
This pin is a logic input referenced to analog ground.
AMPSHDN = low results in normal operation. AMPSHDN
= high results in powered down amplifi er with typically
3mA amplifi er supply current.
MODE (Pin G3): Output Format and Clock Duty Cycle
8
CC
DD
+
–
DD
(Pin G1): Positive (Noninverting) Amplifi er Input.
(Pin H1): Negative (Inverting) Amplifi er Input.
(Pins E1, E2): 3.3V Analog Supply Pin for Amplifi er.
(Pins E5, D5): 3.3V Analog Supply Pin for ADC. This
(Pins A6, G9): Positive Supply for the ADC Output
DD
to select the internal
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty cycle
stabilizer. Connecting MODE to 1/3V
output format and enables the clock duty cycle stabilizer.
Connecting MODE to 2/3V
output format and enables the clock duty cycle stabilizer.
Connecting MODE to V
format and disables the clock duty cycle stabilizer.
RAND (Pin F3): Digital Output Randomization Selection
Pin. RAND = low results in normal operation. RAND =
high selects D1 to D15 to be EXCLUSIVE-ORed with D0
(the LSB). The output can be decoded by again applying
an XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.
PGA (Pin E3): Programmable Gain Amplifi er Control Pin.
PGA = low selects the normal (maximum) input voltage range.
PGA = high selects a 3.5dB reduced input range for slightly
better distortion performance at the expense of SNR.
ADCSHDN (Pin B3): Power Shutdown Pin for ADC.
ADCSHDN = low results in normal operation. ADCSHDN
= high results in powered down analog circuitry and the
digital outputs are placed in a high impedance state.
DITH (Pin A3): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal
dither. Refer to Internal Dither section of this data sheet
for details on dither operation.
OE (Pin F5): Output Enable Pin. Low enables the digital
output drivers. High puts digital outputs in Hi-Z state.
Digital Outputs
D0 to D15 (See Pin Confi guration Table for Pin Locations):
Digital Outputs. D15 is the MSB and D0 the LSB.
CLKOUT
will toggle at the sample rate. Latch the data on the rising
edge of CLKOUT
CLKOUT
toggle at the sample rate. Latch the data on the falling
edge of CLKOUT
OF (Pin G5): Over/Under Flow Digital Output. OF is high
when an over or under fl ow has occurred.
+
–
(Pin E7): Inverted Data Valid Output. CLKOUT
(Pin E6): Data Valid Output. CLKOUT
+
–
.
.
DD
selects 2’s complement output
DD
selects 2’s complement
DD
selects offset binary
–
9001gaf
will
+