ADXL345BCCZ Analog Devices Inc, ADXL345BCCZ Datasheet - Page 24
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ADXL345BCCZ
Manufacturer Part Number
ADXL345BCCZ
Description
IC ACCEL SPI/I2C 3AX 3G 14LGA
Manufacturer
Analog Devices Inc
Series
iMEMS®r
Datasheet
1.EVAL-ADXL345Z.pdf
(40 pages)
Specifications of ADXL345BCCZ
Acceleration Range
±2g, 4g, 8g, 16g
Design Resources
Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133)
Axis
X, Y, Z
Sensitivity
256LSB/g, 128LSB/g, 64LSB/g, 32LSB/g
Voltage - Supply
2 V ~ 3.6 V
Output Type
Digital
Bandwidth
6.25Hz ~ 3.2kHz Selectable
Interface
I²C, SPI
Mounting Type
Surface Mount
Package / Case
14-LGA
No. Of Axes
3
Sensor Case Style
LGA
No. Of Pins
14
Supply Voltage Range
2V To 3.6V
Operating Temperature Range
-40°C To +85°C
Package
14LGA
Acceleration
±2/±4/±8/±16 g
Axis Type
Triple
Operating Supply Voltage
2 to 3.6 V
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADXL345Z - BOARD EVALUATION FOR ADXL345EVAL-ADXL345Z-S - BOARD SATELLITE FOR ADXL345Z-MEVAL-ADXL345Z-M - BOARD EVAL FOR ADXL345
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
Q4372599
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ADXL345
REGISTER DEFINITIONS
Register 0x00—DEVID (Read Only)
D7
1
The DEVID register holds a fixed device ID code of 0xE5 (345 octal).
Register 0x1D—THRESH_TAP (Read/Write)
The THRESH_TAP register is eight bits and holds the threshold
value for tap interrupts. The data format is unsigned, therefore,
the magnitude of the tap event is compared with the value
in THRESH_TAP for normal tap detection. The scale factor is
62.5 mg/LSB (that is, 0xFF = 16 g). A value of 0 may result in
undesirable behavior if single tap/double tap interrupts are
enabled.
Register 0x1E, Register 0x1F, Register 0x20—OFSX,
OFSY, OFSZ (Read/Write)
The OFSX, OFSY, and OFSZ registers are each eight bits and
offer user-set offset adjustments in twos complement format
with a scale factor of 15.6 mg/LSB (that is, 0x7F = 2 g). The
value stored in the offset registers is automatically added to the
acceleration data, and the resulting value is stored in the output
data registers. For additional information regarding offset
calibration and the use of the offset registers, refer to the Offset
Calibration section.
Register 0x21—DUR (Read/Write)
The DUR register is eight bits and contains an unsigned time
value representing the maximum time that an event must be
above the THRESH_TAP threshold to qualify as a tap event. The
scale factor is 625 μs/LSB. A value of 0 disables the single tap/
double tap functions.
Register 0x22—Latent (Read/Write)
The latent register is eight bits and contains an unsigned time
value representing the wait time from the detection of a tap
event to the start of the time window (defined by the window
register) during which a possible second tap event can be detected.
The scale factor is 1.25 ms/LSB. A value of 0 disables the double tap
function.
Register 0x23—Window (Read/Write)
The window register is eight bits and contains an unsigned time
value representing the amount of time after the expiration of the
latency time (determined by the latent register) during which a
second valid tap can begin. The scale factor is 1.25 ms/LSB. A
value of 0 disables the double tap function.
Register 0x24—THRESH_ACT (Read/Write)
The THRESH_ACT register is eight bits and holds the threshold
value for detecting activity. The data format is unsigned, so the
magnitude of the activity event is compared with the value in
the THRESH_ACT register. The scale factor is 62.5 mg/LSB.
A value of 0 may result in undesirable behavior if the activity
interrupt is enabled.
D6
1
D5
1
D4
0
D3
0
D2
1
D1
0
D0
1
Rev. B | Page 24 of 40
Register 0x25—THRESH_INACT (Read/Write)
The THRESH_INACT register is eight bits and holds the threshold
value for detecting inactivity. The data format is unsigned, so
the magnitude of the inactivity event is compared with the value
in the THRESH_INACT register. The scale factor is 62.5 mg/LSB.
A value of 0 may result in undesirable behavior if the inactivity
interrupt is enabled.
Register 0x26—TIME_INACT (Read/Write)
The TIME_INACT register is eight bits and contains an unsigned
time value representing the amount of time that acceleration
must be less than the value in the THRESH_INACT register for
inactivity to be declared. The scale factor is 1 sec/LSB. Unlike
the other interrupt functions, which use unfiltered data (see the
Threshold section), the inactivity function uses filtered output
data. At least one output sample must be generated for the
inactivity interrupt to be triggered. This results in the function
appearing unresponsive if the TIME_INACT register is set to a
value less than the time constant of the output data rate. A value
of 0 results in an interrupt when the output data is less than the
value in the THRESH_INACT register.
Register 0x27—ACT_INACT_CTL (Read/Write)
D7
ACT ac/dc
D3
INACT ac/dc
ACT AC/DC and INACT AC/DC Bits
A setting of 0 selects dc-coupled operation, and a setting of 1
enables ac-coupled operation. In dc-coupled operation, the
current acceleration magnitude is compared directly with
THRESH_ACT and THRESH_INACT to determine whether
activity or inactivity is detected.
In ac-coupled operation for activity detection, the acceleration
value at the start of activity detection is taken as a reference
value. New samples of acceleration are then compared to this
reference value, and if the magnitude of the difference exceeds
the THRESH_ACT value, the device triggers an activity interrupt.
Similarly, in ac-coupled operation for inactivity detection, a
reference value is used for comparison and is updated whenever
the device exceeds the inactivity threshold. After the reference
value is selected, the device compares the magnitude of the
difference between the reference value and the current acceleration
with THRESH_INACT. If the difference is less than the value in
THRESH_INACT for the time in TIME_INACT, the device is
considered inactive and the inactivity interrupt is triggered.
D6
ACT_X enable
D2
INACT_X enable
D5
ACT_Y enable
D1
INACT_Y enable
D4
ACT_Z enable
D0
INACT_Z enable