74HC4046AN NXP Semiconductors, 74HC4046AN Datasheet - Page 31

• Manufacturer Part Number: 74HC4046AN
• Description: IC, 74HC CMOS, 74HC4046, DIP16, 5V
• Manufacturer: NXP Semiconductors

Specifications of 74HC4046AN

• Pll Type: VCO
• Frequency: 21MHz
• Supply Voltage Range: 2V To 6V
• Digital Ic Case Style: DIP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +125°C
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Supply Current: 8µA
• Rohs Compliant: Yes
• Base Number: 74

Philips Semiconductors
PLL design example
The frequency synthesizer, used in
the design example shown in Fig.32,
has the following parameters:
Output frequency: 2 MHz to 3 MHz
frequency steps : 100 kHz
settling time
overshoot
The open-loop gain is
H (s) x G (s) = K
Where:
K
K
K
K
The programmable counter ratio
K
The VCO is set by the values of R1,
R2 and C1, R2 = 10 k (adjustable).
The values can be determined using
the information in the section
“DESIGN CONSIDERATIONS”.
With f
this gives the following values
(V
R1 = 10 k
R2 = 10 k
C1 = 500 pF
1997 Nov 25
N
N
p
f
o
n
n
min.
max.
CC
Phase-locked-loop with VCO
= phase comparator gain
= K
= 1/n divider ratio
can be found as follows:
= low-pass filter transfer gain
= 5.0 V):
o
=
v
=
/s VCO gain
= 2.5 MHz and f
---------- -
f
f
---------- -
f
step
f
step
out
out
=
=
p
--------------------- -
100 kHz
:
:
--------------------- -
100 kHz
2 MHz
3 MHz
K
1 ms
f
20%
L
K
= 500 kHz
o
=
=
20
K
30
n
.
The VCO gain is:
The gain of the phase
comparator is:
The transfer gain of the filter is
given by:
Where:
The characteristics equation is:
1 + H (s)
This results in:
The natural frequency
defined as follows:
K
=
K
K
s
K
------------------------------- -
1
2
v
p
f
p
n
1 MHz
-----------------
+
=
=
=
=
=
1
3.2
1
----------------------------------------------------- s+
K
------------------------------------ - .
1
R3C2 and
+
---------------------------------------------- -
0.9
------------
4
V
+
v
+
K
------------------------------- - .
CC
K
2
1
p
2f
–
K
p
G (s) = 0.
+
n
2
1
1
L
=
1
K
V
K
+
+
=
2
+
CC
v
˙
0.4 V/r.
v
s
2
0.
2
2
2 10
2
31
–
K
K
2
s
n
0.9
n
=
R4C2.
6
n
=
2
r/s/V
is
and the damping value is defined as
follows:
In Fig.33 the output frequency response to
a step of input frequency is shown.
The overshoot and settling time
percentages are now used to determine
damping ratio = 0.45 will produce an
overshoot of less than 20% and settle to
within 5% at
time is 1 ms.
This results in:
Rewriting the equation for natural
frequency results in:
The maximum overshoot occurs at N
When C2 = 470 nF, then
now R3 can be calculated:
R4
R3
n
n
. From Fig.33 it can be seen that the
1
1
=
=
=
=
+
+
---------------------------------------------------------------- -
------- - R4 = 2 k .
C2
--------- -
2
5
-- -
t
2
2
1
1
1
=
n
K
–
+
=
=
p
-------------- -
0.001
1
-----------------------------------------------------
K
------------------------------- - .
0.4 2 10
-------------------------------- -
2
74HC/HCT4046A
5
5000
n
p
K
+
t = 5. The required settling
v
K
2
K
p
=
2
K
v
2
n
5 10
1
n
K
Product specification
30
+
K
n
v
n
C2
6
2
K
3
=
n
–
r/s.
0.0011 s.
1
=
2
315
max
.: