LTC6994CS6-1#TRMPBF Linear Technology, LTC6994CS6-1#TRMPBF Datasheet - Page 19

• Manufacturer Part Number: LTC6994CS6-1#TRMPBF
• Description: IC, TIMERBLOX, SINGLE, 5.5V, 6-TSOT-23
• Manufacturer: Linear Technology

Specifications of LTC6994CS6-1#TRMPBF

• Operating Mode: Monostable
• No. Of Timers: 1
• Clock External Input: No
• Supply Voltage Range: 2.25V To 5.5V
• Digital Ic Case Style: TSOT-23
• No. Of Pins: 6
• Operating Temperature Range: 0°C To +70��C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
Supply Bypassing and PCB Layout Guidelines
The LTC6994 is an accurate monostable multivibrator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Figure 16 shows example PCB layouts for both the SOT-23
and DCB packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6994. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V
GND pins using a low inductance path. The connection
from C1 to the V
layer. For the DCB package, C1’s connection to GND is
also simply done on the top layer. For the SOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
+
pin is easily done directly on the top
R2
R1
SET
DIV
V
V
+
+
R
C1
SET
DCB PACKAGE
Figure 16. Supply Bypassing and PCB Layout
GND
OUT
IN
R
SET
+
and
IN
GND
SET
LTC6994
OUT
2. Place all passive components on the top side of the
3. Place R
4. Connect R
5. Use a ground trace to shield the SET pin. This provides
6. Place R1 and R2 close to the DIV pin. A direct, short
DIV
V
+
board. This minimizes trace inductance.
a direct, short connection. The SET pin is a current sum-
ming node and currents injected into this pin directly
modulate the output delay. Having a short connection
minimizes the exposure to signal pickup.
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
another layer of protection from radiated signals.
connection to the DIV pin minimizes the external signal
coupling.
C1
0.1µF
SET
GND
R
SET
IN
SET
LTC6994-1/LTC6994-2
TSOT-23 PACKAGE
SET
as close as possible to the SET pin and make
R1
R2
directly to the GND pin. Using a long path
V
+
R2
OUT
DIV
C1
V
+
699412 F16
R1
V
+
19
699412f