78Q8430-100CGT/F TERIDIAN, 78Q8430-100CGT/F Datasheet
78Q8430-100CGT/F
Specifications of 78Q8430-100CGT/F
Related parts for 78Q8430-100CGT/F
78Q8430-100CGT/F Summary of contents
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... Parallel/Serial, Manchester Encoder Carrier Sense, Collision Detect Parallel/Serial CLK Recovery Serial/Parallel Descrambler, Clock Reference 5B/4B Decoder CLKIN 25MHz © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transeiver DATA SHEET JANUARY 2006 and power-down modes Pulse Shaper and Filter Tx/Rx Auto MDI-X Mux Rx/Tx ...
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... CDR will use the received MLT- 3 signal as the clock reference. The recovered clock is used to re-time the data signal and for conversion of the data to NRZ format. The on-chip © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver uses an on-chip frequency In 10BASE-T mode, it The signal Rev 1 ...
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... MAC via the Media Independent Interface. through an external 1:1 transformer. information is detected and corrected within internal circuitry. © 2006 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver No external During auto-negotiation and When this timer receive Manchester- ...
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... MR18.12 will reflect this and auto negotiation will restart from the beginning. Writing a ‘1’ to bit MR0.9 (RANEG) will also cause auto- negotiation to restart. during auto- © 2006 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver FUNCTION DEFAULT VALUE Speed Select 1 (100 BASE TX) ...
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... INTR pin. When the INTR pin is not asserted, the pin is held in a high impedance state. An external pull-up or pull-down resistor may be required for use with the INTR pin. © 2006 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver All PHYs sharing the same Interface ...
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... The 78Q2123/78Q2133 default to auto MDIX enabled with parallel detection. MR24.6 and MR24.7 are both defaulted to 1. The 78Q2123/78Q2133 will resolve configuration within 5 seconds. Page enabled, the to the other Register bits the proper © 2006 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver Rev 1.1 ...
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... MR16.0, in which RX_CLK is held inactive (low) when no receive data is detected. This pin is tri-stated in isolate mode. Page TYPE DESCRIPTION CI TTL-level Input CIO TTL-compatible Bi-directional Pin COZ Tristate-able CMOS output G Ground © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver Rev 1.1 ...
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... The pin will be forced high or low to signal an interrupt depending upon the value of the INPOL bit (MR16.14). The events which trigger an interrupt can be programmed via the Interrupt Control Register located at address MR17. Page up) © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver Rev 1.1 ...
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... XTLN 25 A CRYSTAL OUTPUT: Should be connected MHz crystal. When an external clock source is being used, this pin must be grounded. POWER SUPPLY AND GROUND SIGNAL PIN TYPE DESCRIPTION PWR +3.3VDC SUPPLY GND 10 GROUND Page © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver Rev 1.1 ...
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... BASE-T: ON for 10BASE-T connection and OFF for other connections. LEDBT is OFF during auto-negotiation. FULL DUPLEX: ON when in full duplex mode and OFF when in half duplex mode. LINK/ACT: ON for link, blink for activity. Page © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver Rev 1.1 ...
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... Interrupt Control/Status Register Diagnostic Register Transceiver Control Reserved LED Configuration Register MDI/MDIX Control Register TYPE DESCRIPTION W Writeable by management. RC Readable by management. Cleared upon a read operation. © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver DEFAULT (HEX) (3100) (7849) 000E 7237 (01E1) 0000 0000 0000 0000 0000 ...
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... Collision Test: When this bit is set to ‘1’, the device will assert the COL signal in response to the assertion of the TX_EN signal. Collision test is disabled if the PCSBP bit, MR16.1, is high. Collision test can be activated regardless of the duplex mode of operation. 0 Reserved © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver If auto-negotiation is not Rev 1.1 ...
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... Auto-Negotiation Complete: Negotiation process has been completed, and that the contents of registers MR4,5,6 are valid. © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver Reads ‘0’ to indicate the Reads ‘0’ to indicate the A logic one indicates that the Auto- Rev 1.1 ...
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... Extended Capability: provide an extended register set (MR2 and beyond). DESCRIPTION Organizationally Unique Identifier: TERIDIAN Semiconductor Corporation. This register contains the first 16-bits of the identifier. DESCRIPTION 1Ch Organizationally Unique Identifier: Remaining 6 bits of the OUI. 23h Model Number: The last 2 digits of the model number 78Q2123 are encoded into the 6 bits for both 78Q2123 and 78Q2133 ...
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... If the MR1.11 bit is ‘1’, this bit will be set to ‘1’ upon reset and will be writeable. Otherwise, this bit cannot be set to ‘1’ by the management. 01h Selector Field: Hard coded with the value of ‘00001’ for IEEE 802.3. © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver Rev 1.1 ...
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... Reads ‘1’ when a new link code word has been received into the Auto-Negotiation Link Partner Ability Register. This bit is cleared upon read. 0 Link Partner Auto-Negotiation Able: When ‘1’ is read, it indicates the link partner is able to participate in the Auto-Negotiation function. © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver Rev 1.1 ...
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... If Auto Polarity is disabled, then this bit is writeable. Writing a ‘1’ to this bit forces the polarity of the receive signal to be reversed. 0h Reserved: Must set to ‘00’. © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver When set, the TXOP/TXON When the Rev 1.1 ...
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... Parallel Detect Fault Interrupt: This bit is set high by the auto- negotiation logic when a parallel detect fault condition is indicated. © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver This function is valid only in 100Base-TX RXCC is disabled when Rev 1.1 ...
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... Reserved: Must set to ‘00h’. © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver This bit is set when the link This bit is set when a remote fault This bit is set when auto- In 10Base-T mode, this bit Rev 1 ...
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... Gain set for 0.4dB of insertion loss 10 : Gain set for 0.8dB of insertion loss 11 : Gain set for 1.2dB of insertion loss XXXh Reserved: must be 000h. XXXXh Reserved: must be 0000h. XXXXh Reserved: must be 0000h. XXXXh Reserved: must be 0000h. © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver Rev 1.1 ...
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... Full Duplex 1000 = Link OK/Blink= Activity <0h> 0000 = Link OK (Default LED0) 0001 = Activity 0010 = TX Activity 0011 = RX Activity 0100 = Collision 0101 = 100 BASE-TX mode 0110 = 10 BASE-T mode 0111 = Full Duplex 1000 = Link OK/Blink= Activity © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver Rev 1.1 ...
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... Sequence in progress or auto-switch is disabled. <0000> Write initial pattern seed for switching algorithm. seed directly affects attempts [5,4] respectively to write bits [3:0]. Setting to [0000] will result in device using its own seed of [0101]. © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver The initial Rev 1.1 ...
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... Vcc = 3.3V Auto-Negotiation 10BT (Idle) 10BT (Normal Activity) 100BTX Power-down mode I CC © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver RATING -0.5 to 4.0 VDC -65 to 150°C -0.3 to (Vcc+0.6) VDC -0.3 to (Vcc+1.4) VDC ± 120 mA RATING 3.3 ± 0.3 VDC 0 to 70°C -40 to 85° ...
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... Iil, Iih Cin Vhy SYMBOL CONDITIONS Vol Iol = 4mA Voh Ioh = -4mA 20pF L Iz SYMBOL CONDITIONS Vol Iol = 4mA Voh Ioh = -4mA 20pF L © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver MIN NOM MAX 0.8 2.0 3 MIN NOM MAX 2.0 0 125 MIN NOM MAX 0 ...
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... RSTN Pulse Assertion Page SYMBOL CONDITIONS Vol Iol = 4mA Voh Ioh = -4mA 20pF L RSTN Pulse Duration SYMBOL CONDITIONS Treset VCC = 3.3V and oscillator stabilized © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver MIN NOM MAX 0.4 2.4 T reset MIN NOM MAX 30 UNIT UNIT ...
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... SYMBOL CONDITIONS CKIN CKIN TX SU TX_CLK TXD[3:0] TX_EN or TX_ER Transmit Inputs to the 78Q2123/78Q2133 SYMBOL CONDITIONS RX DLY RX DLY (MAX) RX (MIN) Receive Outputs from the 78Q2123/78Q2133 © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver MIN NOM MAX CKIN TX HD MIN NOM MAX DLY UNIT ...
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... MIO SU MIO HD F max MDC MIO SU MDIO MDIO as an Input to the 78Q2123/78Q2133 SYMBOL CONDITIONS MC2D MCZ2D MCD2Z MC2D MDIO as an Output from the 78Q2123/78Q2133 © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver MIN NOM MAX MIO HD MIN NOM MAX MCD2Z UNIT ns ns ...
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... MDIO Interface Output Timing Page © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver Rev 1.1 ...
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... Collision delay SQE test wait SQE test duration Jabber on-time* Jabber off-time* * Guarantee by design. The specifications in the following table are included for information only. Page CONDITION RPTR = low RPTR = low CONDITION MIN 20 250 © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver NOM UNIT ...
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... Vp+, Vp- |tr - tf| Deviation from best-fit time-grid; 010101... Sequence Scrambled Idle TLA-6T103 100Ω ±1% CONDITION 2 < f < 30 MHz 30 < f < 60 MHz < f < 80 MHz -8 < Iin < © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver NOM MAX UNIT 1050 mVpk 1. 500 ps ±250 ps 1 ...
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... Not tested CONDITION MIN All data patterns 2.2 Any harmonic 27 All ones data Not tested Last bit 0 Last bit 1 TLA-6T103 100Ω ±1% © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver NOM MAX UNIT 600 700 mVppd 350 425 mVppd 20 kΩ 4 ...
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... MHz sine pk wave applied to transmitter common- mode. All data sequences. CONDITION MIN 30 500 275 Square wave 25 0 < f < 500 kHz Not tested © 2006 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver NOM MAX UNIT dB dB f log 10 ...
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... R14 49.9 C13 C14 27pF 27pF C15 R24 C13 and C14 must be calibrated 10k in actual application board for 0.1uF 25.000MHz +/-50ppm. Application Diagram for 78Q2123/78Q2133 © 2005 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver VCC INTR R9 VCC 49 0.01uF 0.1uF ...
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... Vrms VALUE 25.00000 4** ±50 ±2 ±5 Parallel Resonance, Fundamental Mode 50-100 > below main within 500 kHz © 2006 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver CONDITION @ 10 mV, 10 kHz @ 1 MHz (min MHz UNITS MHz pF PPM PPM/yr PPM µ Ω ...
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... XTLP T clkper T clkhi External XTLP Oscillator Characteristics CONDITION See specification for CIS-type input See Note 1 See Note 1 Tclkhi / Tclkper Input signaling requirements = CIS © 2006 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver MIN NOM MAX 0.8 25.000 4.0 0.1 UNIT V ...
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... PACKAGE PIN DESIGNATIONS (Top View) MDIO MDC LED1 LED0 RXD3 RXD2 RXD1 RXD0 Page TERIDIAN 4 78Q2123 5 78Q2133 © 2006 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver 24 XTLP 23 RSTN 22 CRS 21 COL 20 TXD3 19 TXD2 18 TXD1 17 TXD0 Rev 1.1 ...
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... MIN. 0.3 / 0.5 Page 0.85 NOM. 0.65 NOM. 2.5 2.375 2.95 / 3.25 0.18 / 0.3 1.475 / 1.625 0.5 BOTTOM VIEW © 2006 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver / 0.9MAX. 0.00 / 0.005 / 0.7MAX. 0.20 REF. 12º MAX SEATING PLANE SIDE VIEW ...
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... Note 2: Soldering of bottom internal pad not required for proper operation of either commercial or industrial temperature rated versions. Page DESCRIPTION MIN Lead pitch See Note 1 3.93 mm © 2006 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver TYP MAX 0.5 mm 0.28 mm 0. 3.78 mm Rev 1.1 ...
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... January 2006 No responsibility is assumed by Teridian Semiconductor Corporation for use of this product or for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Teridian Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice ...