78Q8430-100CGTR/F Maxim Integrated Products, 78Q8430-100CGTR/F Datasheet
78Q8430-100CGTR/F
Related parts for 78Q8430-100CGTR/F
78Q8430-100CGTR/F Summary of contents
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... TM Simplifying System Integration DESCRIPTION The Teridian 78Q8430 is a 10/100 Fast Ethernet controller supporting multi-media offload. The device is optimized for host processor offloading and throughput enhancements for demanding multi-media applications found in Set Top Box, IP Video and Broadband Media Appliance applications. The 78Q8430 seamlessly ...
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... Data Sheet 1 Introduction ......................................................................................................................................... 7 1.1 Systems Applications ................................................................................................................... 7 1.2 System Level Application Information .......................................................................................... 8 1.2.1 Set Top Box Application .................................................................................................. 8 1.2.2 IP Security Application ..................................................................................................... 8 1.2.3 IP PBX Application ........................................................................................................... 9 1.3 Overview ...................................................................................................................................... 9 1.4 Application Environments .......................................................................................................... 10 1.5 Supply Voltages ......................................................................................................................... 10 1.6 Power Management ................................................................................................................... 10 2 Pinout ................................................................................................................................................. 11 3 Pin Description .................................................................................................................................. 12 3.1 Pin Legend ................................................................................................................................. 12 3 ...
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... Packet Size Register ..................................................................................................... 56 7.5.3 Setup Transmit Data Register ....................................................................................... 57 7.5.4 Transmit Data Register .................................................................................................. 57 7.5.5 Receive Data Register ................................................................................................... 57 7.5.6 QUE First/Last Register ................................................................................................. 58 7.5.7 QUE Status Register ..................................................................................................... 58 7.6 CTL Registers ............................................................................................................................ 59 7.6.1 DMA Control and Status Register .................................................................................. 59 7.6.2 Receive Packet Status Register .................................................................................... 59 Rev. 1.2 78Q8430 Data Sheet 3 ...
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... Data Sheet 7.6.3 Transmit Packet Status Register ................................................................................... 59 7.6.4 Transmit Producer Status .............................................................................................. 60 7.6.5 Receive Producer Status ............................................................................................... 60 7.6.6 Revision ID ..................................................................................................................... 61 7.6.7 Configuration .................................................................................................................. 61 7.6.8 Receive to Transmit Transfer Register .......................................................................... 61 7.6.9 Frame Disposition Register ........................................................................................... 61 7.6.10 Receive FIRST BLOCK Status Register ....................................................................... 61 7.6.11 Receive Data Status Register ........................................................................................ 62 7 ...
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... Table 31: Process Length/Type, MAC Control Frames and Start IP Header Checksum Rules ................. 42 Table 32: Process Rules for OnNow Packet ............................................................................................... 43 Table 33: Process Rules for Magic Packet ................................................................................................. 43 Table 34: PHY Register Group ................................................................................................................... 74 Table 35: Isolation Transformers ................................................................................................................ 83 Table 36: Reference Crystal ....................................................................................................................... 83 Table 37: 78Q8430 Order Numbers and Packaging Marks ........................................................................ 87 Rev. 1.2 78Q8430 Data Sheet 5 ...
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... Data Sheet Figures Figure 1: 78Q8430 Block Diagram ................................................................................................................ 7 Figure 2: Set Top Box Diagram .................................................................................................................... 8 Figure 3: Network Cameras Diagram ........................................................................................................... 8 Figure 4: Typical FXO VoIP Application ........................................................................................................ 9 Figure 5: Device Block Diagram ................................................................................................................... 9 Figure 6: GBI Bus Block Diagram ............................................................................................................... 10 Figure 7: Pinout ........................................................................................................................................... 11 Figure 8: Host Interface Timing Diagram .................................................................................................... 22 Figure 9: Host Bus Output Timing Diagram ................................................................................................ 23 Figure 10: Host Bus Input Timing Diagram ...
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... The 78Q8430 operates from a single 3.3 V supply. Power down modes and power saving modes are available. The 78Q8430 defaults to use an on-chip crystal oscillator. In this mode MHz reference crystal is connected between the XTLP and XTLN pins. Alternatively, an externally generated 25 MHz clock can be connected to the XTLP pin ...
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... Data Sheet 1.2 System Level Application Information This section provides an overview of system level applications in some typical high-volume consumer equipment. 1.2.1 Set Top Box Application Figure 2 shows a typical application diagram for a set top box. 1.2.2 IP Security Application Figure 3 shows a typical application diagram for an IPTV security camera application. ...
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... IP PBX Application Figure 4 shows a typical application diagram for an IP PBX application. Figure 4: Typical FXO VoIP Application 1.3 Overview The 78Q8430 is divided into four sections, as shown in Figure 5. • Generic Bus Interface (GBI) Control Layer • Queue Memory Layer • Ethernet Media Access Control (MAC) Layer • ...
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... On-chip power converters generate 1.8 V power for core digital logic and memory blocks. The voltage regulator is not affected by the power-down mode. 1.6 Power Management The 78Q8430 supports both normal and power-saving modes. When the GBI bus is active, it can be in normal mode or Power Management low-power modes. 10 78Q8430 ...
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... DS_8430_001 2 Pinout The 78Q8430 is available in a 14x14 mm 100-pin LQFP package. BOOTSZ0 1 GND 2 TMS 3 TDI 4 TRST 5 TCLK 6 RESET 7 VCC 8 ADDR1 9 ADDR0 MEMWAIT 13 GND 14 BUSCLK VCC 17 ADDR2 18 ADDR3 19 ADDR4 20 ADDR5 21 ADDR6 22 ADDR7 23 ADDR8 24 ADDR9 25 Rev. 1.2 78Q8430 Figure 7: Pinout 78Q8430 Data Sheet 75 PROMCS ...
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... Data Sheet 3 Pin Description 3.1 Pin Legend Table 1 lists the different pin types found on the 78Q8430 device. The Type field of the pin description tables refers to one of these types. Type 3.2 Pin Descriptions The pin descriptions in the following tables are grouped by interface. A pin number, type specification per Table 2 and a functional description is provided for each pin on the 78Q8430 device ...
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... This is compatible with the slowest commercial parts, which specify a maximum frequency of 1 MHz. I EEPROM Data In Data line for transmitting from the external EEPROM to the controller. Must be high with no EEPROM present. OZ EEPROM Data Out Transfers data from the controller to an external EEPROM/ROM. 78Q8430 Data Sheet 13 ...
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... Data Sheet 3.2.5 GBI Data Pins Signal Pin Number Type DATA31 69 B DATA30 68 DATA29 67 DATA28 66 DATA27 65 DATA26 64 DATA25 63 DATA24 62 DATA23 59 DATA22 58 DATA21 57 DATA20 56 DATA19 55 DATA18 54 DATA17 53 DATA16 52 DATA15 49 DATA14 48 DATA13 47 DATA12 46 DATA11 45 DATA10 42 DATA9 41 DATA8 40 DATA7 39 DATA6 38 DATA5 33 DATA4 32 DATA3 ...
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... WAITMODE is high then the pin is asserted high; when WAITMODE is low then the pin is asserted low. OD Interrupt (active low) The 78Q8430 asserts the INT signal low when it detects an interrupt event. OD Power Management Event (active low) The 78Q8430 asserts the PME signal low when it detects a wake-up event. 78Q8430 Data Sheet 15 ...
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... Data Sheet 3.2.8 Mode Pins Signal Pin Number BUSMODE 83 CLKMODE 85 WAITMODE 84 ENDIAN0 79 ENDIAN1 80 BOOTSZ1 100 BOOTSZ0 1 Notes: 1. The internal PHY should never be powered down when the internal system clock is selected by the CLKMODE pin (CLKMODE=1) 2. There is no external visibility for the system clock when the internal clock mode is selected. The GBI interface must therefore always be used in asynchronous bus mode ...
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... DS_8430_001 3.2.10 Power Pins Signal Pin Number VCCA VCC 36- GND 34- Rev. 1.2 Table 11: Power Pin Descriptions Type S 3.3 V supply for the analog transmit section. S 3.3 V supply for the digital logic section. G Common ground return. 78Q8430 Data Sheet Description 17 ...
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... Data Sheet 4 Electrical Specification 4.1 Absolute Maximum Ratings Operation above the maximum rating may permanently damage the device. Parameter DC Supply Voltage ( Storage Temperature Pin Voltage (except TXOP/N and RXIP/N) Pin Voltage (TXOP/N and RXIP/N only) Pin Current 4.2 Recommended Operation Conditions Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges ...
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... R F Deviation from best-fit time-grid; 010101... Sequence Scrambled Idle, Internal Oscillator Mode Conditions 2 < f < 30 MHz 30 < f < 60 MHz 16 60 < f < 80 MHz -8 < I < 78Q8430 Data Sheet Nom Max Unit – – 0.8 – – µA – 1 – 8 – pF – ...
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... Data Sheet 4.5.3 100Base-TX Receiver Table 18: MII 100Base-TX Receiver Timing Parameter Signal Detect Assertion Threshold Signal Detect De-assertion Threshold Differential Input Resistance Jitter Tolerance (pk-pk) Baseline Wander Tracking Signal Detect Assertion Time Signal Detect De-assertion Time 4.5.4 10Base-T Transmitter Table 19: MII 10Base-T Transmitter Timing ...
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... Input Unsquelched Threshold Differential Input Resistance Bit Error Ratio Common-mode Rejection Rev. 1.2 Conditions Min – 30 500 275 – – Square wave 25 0 < f < 500 kHz Not tested 78Q8430 Data Sheet Nom Max Unit 10 – BT – – ns 600 700 mVppd 350 425 mVppd 20 – ...
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... Data Sheet 5 Host Interface Timing Specification 5.1 Host Interface CS WR/OE MEMWAIT ADDR DATA Figure 8: Host Interface Timing Diagram Name Description CS and ADDR setup time Output settling time SL T Maximum wait time WT T Wait hold time HWT CS hold time T HCS T ADDR and DATA hold time ...
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... CSB min low CSB min high Rev. 1.2 BUSCLK Output Delay T FALL T Output RISE Delay T SU Symbol Min – FALL T – RISE 78Q8430 Data Sheet T H Nom Max Unit – – ns – – ns – – – – clk – – clk 23 ...
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... Data Sheet 5.1.2 Bus Clock Timing T HIGH Parameter Symbol BUSCLK Cycle Time T CYC BUSCLK Frequency – BUSCLK High Time T HIGH BUSCLK Low Time T LOW BUSCLK Slew Rate – 5.1.3 Reset Timing Parameter RESETB Minimum Duration 24 T CYC 80% 50% 20% T LOW ...
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... Internal Digital Block Figure 12 presents an overview of the functional layers of the 78Q8430. On the left side are the signals, which connect to the GBI bus. On the upper and middle right, the blocks that implement the MAC side of the MII are shown. These blocks are connected to the embedded PHY. On the lower right, connections to the EEPROM are shown ...
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... Data Queuing Ethernet frame data in the 78Q8430 is managed in queuing structures called QUEs. The host bus address space allocated for QUEs has enough space for eight, while the 78Q8430 circuit only implements five. QUEs are identified numerically, QUE0 through QUE7, based on the registers in the QUE register space that are used to access them ...
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... As each frame egresses the transmit FIFO, its status is placed in the transmit status FIFO. Transmit frame status is recovered by reading the Transmit Packet Status Register (TPSR). The Packet ID field from the PCWR is also placed in the TPSR such that the status can be associated with the exact frame to which it belongs. Rev. 1.2 78Q8430 Data Sheet 27 ...
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... Data Sheet 6.3.2.1 Using the Setup Transmit Data Register The Setup Transmit Data Register (STDR) can be used to control the way in which 32-bit data words are transferred to the transmit FIFO. The STDR can be changed on a word-by-word basis to change the network endianness or buffer-byte-alignment, or the STDR can be used to setup the transfer of an entire buffer of transmit data ...
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... FIRST BLOCK in QUE0 is then written to the SNCR register. Now that the SNCR Register has programmed the SNOOP interface to point to the FIRST BLOCK for QUE0, accessing registers in the address space from 0x300 to 0x3FF will be directly accessing the data for the first frame contained in QUE0. Rev. 1.2 78Q8430 Data Sheet 29 ...
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... Data Sheet Snooping the contents of a frame before it is read out of the receive QUE can be useful if additional inspection of the frame is needed, beyond what is provided by classification, to determine the disposition of a received frame. It can also be used, in conjunction with the QUE transfer feature, to minimize host bus overhead in responding to simple ARP or ICMP requests ...
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... The CCR Address field value is automatically incremented after each read or write access to the CDR allowing many counters to be accessed through repeated reads or writes on the CDR without the need to reconfigure the CCR each time. When writing a value to a counter countable event occurs at the Rev. 1.2 Counter Description 78Q8430 Data Sheet 31 ...
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... Data Sheet same time then the actual value placed into the counter is the CDR value plus one to prevent the loss of any countable events. 6.6.3 Precision Counting Applications that require a high degree of temporal precision across all the counters can use the CMR for this purpose ...
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... In other words, a CAM rule with a specified value for the previous hit of zero will only match the first byte of the frame. Rev. 1.2 Control Signals WCS Reference Word CAM Address Figure 14: Classification Architecture 78Q8430 Data Sheet CAM 33 ...
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... Data Sheet 6.7.1 Address Filtering The 78Q8430 CAM is loaded upon reset with a set of default rules for users who only want to use the address filter feature (see Section address-filtering functionality. They support four multicast and eight unicast address filters. The last unicast address filter rule is configured by default as a promiscuous mode rule such that the address-filter is in promiscuous mode right out of reset ...
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... Retain default: 0 Retain default: NOP Retain default: MD Value to write 0x30+N Value of MAC address byte [5] Value of mask byte [5] Set to the CAM rule that was used for byte [4] (0x40+N). 0x7F Retain default: 0x00 Retain default: 0 Set to TAX Retain default: MD 78Q8430 Data Sheet byte [4]: 0x40+N 35 ...
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... Data Sheet STEP 4. Enable the filter. The unicast address filter is enabled by setting the Previous Hit Mask field of the CAM rule for byte [0] to 0x7F. This step must be done last to prevent an ingressing frame from matching a partial set of filter rules. All the rules for a filter must be in place before enabling the filter ...
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... Retain default Retain default: NOP Retain default: MD Value to write 0x3C+N Value of MAC address byte [5] Value of mask byte [5] Set to the CAM rule that was used for byte [4] (0x48+N). 0x7F Retain default: 0x00 Retain default Set to TAX Retain default: MD 78Q8430 Data Sheet byte [4]: 0x48 ...
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... Data Sheet 6.7.2 Configuring the CAM The CAM rules are accessed indirectly one at a time via the CAM Address Register (CAR). The contents of the rule whose number is indicated by the CAR are available for read and write via the Rule Match Register (RMR) and the Rule Control Register (RCR) ...
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... User field. If the value is greater than or equal to 0x0600, the type interpretation used. 6.7.4 Default CAM Rule Summary This section provides the default rules that the 78Q8430B CAM is loaded with on reset. Rev. 1.2 Action Taken Table 27: RCR Match Control ...
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... Data Sheet 6.7.4.1 Destination Address Table 29 contains the rules processing destination address, which also includes the pause packet and promiscuous mode. Table 29: Process Destination Address Rules Rule# PrevHit PH-Mask Data 0x7F 0x00 0x7F 0x7E 0x00 0x00 0x7D 0x00 0x7F 0x7C ...
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... MD 0x00 0x00 0x00 MD 0x00 0x00 0x00 MD 0x00 0x00 0x00 MD 0x00 0x00 0x00 MD 0x00 0x00 0x00 MD 0x00 0x00 0x00 MD 0x00 78Q8430 Data Sheet Action Interrupt Comment NOP 0 NOP 0 NOP 0 NOP 0 NOP 0 NOP 0 NOP 0 NOP 0 NOP 0 NOP 0 NOP 0 NOP 0 TAX 0 ...
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... Data Sheet 6.7.4.2 Source Address Filtering Source address filtering can be used to drop frames with a specific address while passing all others. Table 30 contains the rules on processing source address. Table 30: Process Source Address Rules Rule# PrevHit PH-Mask 0x2F 0x30 0x70 0x2E 0x30 0x70 6 ...
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... MD 0x00 0x30 0xFF MD 0x00 0x40 0xFF MD 0x00 0x50 0xFF MD 0x00 0x60 0xFF MD 0x00 0x00 0x00 DONE 0x00 78Q8430 Data Sheet Action Interrupt Comment NOP 0 NOP 0 NOP 0 NOP 0 NOP 0 WAKE 0 Interrupt Comment TOC 0 Bare Ethernet TOC 0 IP payload TOC ...
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... Data Sheet 6.8 Timers The Timers block implements several timers used within the system. Watermarking for main memory is also handled in this block as it relates to the PAUSE operation. 6.8.1 PAUSE Timer The PAUSE timer is used to implement the MAC Control PAUSE operation described in Annex 31B of IEEE STD 802 ...
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... MAC has to wait in case of a collision, and n is the number of attempts. For example, after the first collision and random number between 0 and 1. The pseudo-random-number generator in this case is one-bit wide and gives a random number of either 0 or Rev. 1.2 78Q8430 Data Sheet 45 ...
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... If there is a collision after the first 64 bytes reported as a late collision and the packet is terminated with an error indication. The 78Q8430 does not retry late collisions. If there are no collisions, the MAC transmit block transmits the rest of the packet and at this time (after the first 64 bytes have been transmitted without collisions), it allows the DMA engine to overwrite this packet ...
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... If a collision occurs after this time a possible network problem is detected. Late collision sets the Late Collision bit in the Transmit Packet Status Register (TPSR) and transmission of the packet is aborted, i.e. late collisions are not retried. Rev. 1.2 78Q8430 Data Sheet 6.3.2.2 for a discussion on how to 47 ...
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... Data Sheet 6.11.1.5 Signal Quality Error In 10 Mbps mode, the MAC checks for a “heartbeat” at the end of a transmitted packet. This is a short Collision signal within the first 40 bit times after end of transmission. Signal Quality Error sets the No Heart Beat bit in the Transmit Packet Status Register (TPSR). ...
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... The 78Q8430 PHY can compensate for cable loss 10dB at 16 MHz. This loss is represented as test_chan_5 in Annex A of the ANSI X3.263:1995 specification and corresponds to approximately 140 m of CAT-5 UTP cabling ...
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... SQE Test The 78Q8430 PHY supports the signal quality error (SQE) function detailed in IEEE-802. interval of 1µs after each negative transition of the TXEN pin in 10BASE-T mode, the COL pin will go high for a period of 1µs. SQE is not signaled if a collision is detected during transmission. This function can be disabled through register bit MR16 ...
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... At the same time, it will look for either 10BASE-T idle, 100BASE-TX idle or fast link pulses from its link partner. If either idle pattern is detected, the 78Q8430 PHY configures itself in half- duplex mode at the appropriate speed detects fast link pulses, it decodes and analyzes the link code transmitted by the link partner ...
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... Register Descriptions 7.1 Register Overview The 78Q8430 has 10 address bits for a total address space of 1024 bytes. This address space is divided into four 256-location blocks: QUE, CTL, Reserved and SNOOP. The QUE section contains registers used to control transmit and receive queues. Each queue is allocated eight 32-bit registers for a maximum of eight queues supported ...
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... Packet Size Register STDR Setup Transmit Data Register TDR Transmit Data Register RDR Receive Data Register Reserved QFLR QUE First/Last pointers. QSR QUE Status Register QUE 1 Registers QUE 2 Registers QUE 3 Registers QUE 4 Registers QUE 5 Registers QUE 6 Registers QUE 7 Registers 78Q8430 Data Sheet 53 ...
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... Data Sheet 7.3 CTL Register Overview Address Symbol Page 0x100 DMA 59 0x104 RPSR 59 0x108 TPSR 59 0x10C TPROS 60 0x110 RPROS 60 0x114 Reserved 0x118 GBI_ID 61 0x11C GBI_CS 61 0x120 Reserved 0x124 Reserved 0x128 RTTR 61 0x12C FDR 61 0x130 RFBSR 61 0x134 RDSR 62 0x138 BCR 62 0x13C ...
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... Transmit RMON Interrupt Register Transmit RMON Mask Register Receive RMON Interrupt Register Receive RMON Mask Register Host Interrupt Register Host Interrupt Mask Register Accessing data in this address space will be mapped to the contents of the buffer memory BLOCK indicated by the SNCR. 78Q8430 Data Sheet 55 ...
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... Data Sheet 7.5 QUE Registers 7.5.1 Packet Control Word Register Name: PCWR Reset Val: 0x0000_0000 Bits Type Default Description 31:30 X Reserved 29:25 WO N/A Preload The number of bytes to pre-load into the MAC TX FIFO before the frame begins transmission to the PHY. This may need to be non-zero for large IP headers that want to have the checksum inserted to ensure the checksum is not transmitted before the end of the header is loaded ...
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... Packet Data Read from the QUE Data read from this register is shifted out of the QUE to which the register belongs. The RPSR should be consulted to make sure data is available before reading this register. Rev. 1.2 78Q8430 Data Sheet Block: QUE Address: 0x008 Block: QUE Address: 0x00C ...
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... Data Sheet 7.5.6 QUE First/Last Register Name: QFLR Reset Val: 0x0000_0000 Bits Type Default Description 31:23 X Reserved 22:16 RW 0x00 Last The value of the Last pointer for this QUE. 15:7 X Reserved 6:0 RW 0x00 First The value of the First pointer for this QUE. ...
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... When not set, the frame is still in transmission. When set, the content is egressing the QUE Halted The packet was halted Truncated The packet was truncated and is incomplete. Rev. 1.2 78Q8430 Data Sheet Block: CTL Address: 0x100 Block: CTL Address: 0x104 Block: CTL Address: 0x108 59 ...
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... Data Sheet Name: TPSR Reset Val: 0x0E00_0000 Bits Type Default Description Carrier Loss of carrier during transmission. 27: QUE The number of the QUE that was the source for this packet. 24: Packet ID The packet ID that was assigned to this packet by the PCWR when it was loaded into the QUE. ...
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... Next The BLOCK that is next in QUE0 after the current FIRST BLOCK. 7 Used The number of valid bytes in the FIRST BLOCK for QUE0. Rev. 1.2 78Q8430 Data Sheet Block: CTL Address: 0x118 Block: CTL Address: 0x11C Block: CTL Address: 0x128 Block: CTL Address: 0x12C ...
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... Data Sheet 7.6.11 Receive Data Status Register Name: RDSR Reset Val: 0x0001_0000 Bits Type Default Description 31:25 Reserved EOF When set this bit indicates that the next data word read from QUE0 will be the end of its frame. 23:17 Reserved QUE0 Empty When set this bit indicates that QUE0 contains no data ...
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... Reset Val: 0x0000_0000 Bits Type Default Description 31:16 X 0000 Reserved 15:0 RW 0000 PROM Data Data to write to or read from the EEPROM device. Rev. 1.2 78Q8430 Data Sheet Block: CTL Address: 0x13C Block: CTL Address: 0x140 Block: CTL Address: 0x144 Block: CTL Address: 0x148 63 ...
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... Data Sheet 7.6.17 PROM Control Register Name: PRCR Reset Val: 0x0000_0000 Bits Type Default Description 31:9 X 0000 Reserved Busy Writing a 1 initiates the EEPROM data transfer. The hardware will clear the bit when the operation completes. 7:6 RW 0x0 Operation Erase. ...
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... When this bit is clear, the CDR is in read mode. When set, the CDR is in write mode. 7:6 X Reserved 5:0 RW Address Address of the counter to access. (00 to 0E, Transmit Counters 25, Receive Counters) Rev. 1.2 78Q8430 Data Sheet Block: CTL Address: 0x164 Block: CTL Address: 0x168 65 ...
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... Data Sheet 7.6.21 Counter Management Register Name: CMR Reset Val: 0x0000_0000 Bits Type Default Description 31:3 X Reserved 2 RW Freeze When this bit is set, the values of the counters are frozen until the bit is cleared. Countable events that occur while this bit is set are stored in a FIFO and processed after the bit is cleared such that no counts are lost ...
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... Reads back 1 to indicate the clock (BUSCLK) is needed for PME operation. 18:16 RO 010 VER Reads back 010b to indicate specification version 1.1 compliance. Rev. 1.2 78Q8430 Data Sheet Block: CTL Address: 0x188 Block: CTL Address: 0x18C Block: CTL Address: 0x190 Block: CTL ...
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... Data Sheet Name: PMCAP Reset Val: 0x120A_4801 Bits Type Default Description 15:8 RO 0x48 Next Reads back 0x48. Points to next capability. 7:0 RO 0x01 ID Reads back 0x01. 7.6.29 Power Management Control and Status Register Name: PMCSR Reset Val: 0x0000_0000 Bits Type Default ...
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... TXA 0x12 = TLXA Rev. 1.2 Block: CTL Address: 0x1A4 Block: CTL Address: 0x1A8 0x14 = THXA 0x15 = SETMC 0x16 = VLAN 0x17 = SETBC 0x18 = TOC 0x1A = DEC 0x1B = MCTL 0x1C = TDPH 0x1D = TDLTH 0x1E = TDPL 0x1F = TDLTL 78Q8430 Data Sheet Table 26. 69 ...
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... Data Sheet Name: RCR Reset Val: 0x0000_0002 Bits Type Default Description 1 Match Control How to generate a CAM reference word for the next pass. Match control is described in detail DONE DROP 7.6.33 Que Status Interrupt Register Name: QSIR Reset Val: 0x0000_0000 Bits Type ...
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... RMON Tx Counter Rollover 0000 Set when the RMON Tx counter with the same index number as the bit number has rolled over. Note: All bits are cleared on read. Rev. 1.2 78Q8430 Data Sheet Block: CTL Address: 0x1C8 Block: CTL Address: 0x1CC Block: CTL ...
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... Data Sheet 7.6.38 Transmit RMON Mask Register Name: TRMR Reset Val: 0x0000_0000 Bits Type Default Description 31:0 RW 0x0000 Tx RMON Interrupt Mask 0000 When a bit is set, it enables the Tx RMON interrupt for the corresponding bit in the TRIR. When a bit is clear, the corresponding bit in the TRIR will still be set on its event and cleared on read but will not be passed on to the HIR ...
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... When a bit is set here it enables the host interrupt for the corresponding bit in the HIR. When a bit is clear here, the corresponding bit in the HIR will still be set on its event and cleared on read but will not trigger an interrupt on INT. Rev. 1.2 78Q8430 Data Sheet Block: CTL Address: 0x1E8 Block: CTL Address: 0x1EC ...
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... PHY Management Registers 7.7.1 PHY Register Overview The 78Q8430 PHY implements sixteen-bit registers which are accessible via the MAC Station Management Access Registers. The supported registers are shown below. Unsupported registers will be read as all zeroes. The 78Q8430 PHY responds to PHYAD value 00001b. ...
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... PHY. Setting this bit to 1 indicates 100Base-TX operation and a 0 indicates 10Base-T mode. This bit will default to 1 upon reset. When auto-negotiation is enabled, this bit will not be writable and will have no effect on the 78Q8430 PHY. If auto-negotiation is not enabled, this bit may be written to force manual configuration. ...
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... Data Sheet 7.7.3 PHY Status Register – MR1 MR1 bits 15 through 11 reflect the ability of the 78Q8430 PHY. They do not reflect any ability changes made via the MII Management interface to MR0 bits 13 (SPEEDSL), 12 (ANEGEN) and 8 (DUPLEX). Bits Symbol Type 15 100T4 R 14 ...
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... In 10Base-T mode, this bit is set during a jabber event. After the event, the bit remains set until cleared by a read operation. 1 Extended Capability Reads 1 to indicate the 78Q8430 PHY provides an extended register set (MR2 and beyond). Value Description 000Eh Organizationally Unique Identifier This value is 00-C0-39 for Teridian Semiconductor Corporation ...
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... Link Partner Next Page Able When 1 is read, it indicates the link partner supports the Next Page function. 0 Next Page Able Reads 0 since the 78Q8430 PHY does not support the Next Page function. 0 Page Received Reads 1 when a new link code word has been received into the Auto-negotiation Link Partner Ability Register ...
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... When the reverse polarity is detected and if the Auto Polarity feature is enabled, the 78Q8430 PHY will invert the receive data input and set this bit Auto Polarity is disabled, then this bit is writeable. Writing this bit forces the polarity of the receive signal to be reversed ...
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... Data Sheet 7.7.9 PHY Interrupt Control / Status Register – MR17 The Interrupt Control/Status Register provides the means for controlling and observing the events that trigger an interrupt on the internal PHY interrupt signal. This register can also be used in a polling mode via the MII Serial Interface as a means to observe key events within the PHY via one register address. ...
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... BASE-TX mode 0110 = 10 BASE-T mode 0111 = Full Duplex 1000 = Link OK/Blink= Activity <0h> 0000 = Link OK (Default LED0) 0001 = Activity 0010 = TX Activity 0011 = RX Activity 0100 = Collision 0101 = 100 BASE-TX mode 0110 = 10 BASE-T mode 0111 = Full Duplex 1000 = Link OK/Blink= Activity 78Q8430 Data Sheet 81 ...
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... Data Sheet 7.7.13 PHY MDI / MDIX Control Register – MR24 Bit Symbol Type 15 PD_MODE R/W 6 AUTO_SW R/W 5 MDIX R/W 4 MDIX_CM R 3:0 MDIX_SD R/W 82 Default Description 0 Unused 1 Parallel Detect Mode Write this bit to add Parallel Detect mode. This will allow auto-switching to work when auto-negotiation is off while the other device has it on ...
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... Vrms Table 36: Reference Crystal Value 25.00000 4** ≤ ±50 per IEEE 802.3 requirement Parallel Resonance, Fundamental Mode Drive Level = 0 > below main within 500 kHz 78Q8430 Data Sheet Condition @ 10 mV, 10 kHz @ 1 MHz (min MHz Units MHz pF PPM pF pF Ω 83 ...
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... Data Sheet 10 System Bus Interface Schematic ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 RESET BUSCLK MEMWAIT INT PME ENDIAN1 ENDIAN0 BOOTSZ1 BOOTSZ0 BUSMODE CLKMODE WAITMODE PROMCLK Optional PROMCS External PROMDO EEPROM PROMDI BOOTSZ[1: bus is 32-bit wide 01 - bus is 16-bit wide ...
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... MHz Parallel Resonant Figure 16: Line Interface Schematic 78Q8430 Data Sheet 680Ω A Link LED C A LED Activity C 1:1 Transformer 50Ω +3.3VA +3.3VA 0.1µ 0.1µ ...
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... Data Sheet 12 Package Mechanical Drawing (100-pin LQFP) 1 0.60(0.024) TYP. 0.18(0.007) 0.27(0.011) 86 Top View 15.70 (0.618) 16.30 (0.641) LQFP 100 Side View 13.80 (0.543) 14.20 (0.559) 1.40(0.055) 1.60(0.063) 0.50(0.020)TYP. Figure 17: LQFP Drawing DS_8430_001 0.05(0.002) 0.15(0.006) Rev. 1.2 ...
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... ARM9(920T) Embest Evaluation Board User Manual 78Q8430 ARM9(920T) Linux Driver Diagnostic Guide Check the website for the latest versions of these documents. 15 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 78Q8430, contact us at: 6440 Oak Canyon Road Suite 100 ...
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... Data Sheet Revision History Revision Date 1.0 7/21/2008 First publication. 1.1 1/21/2009 Removed 128-pin package. 1.2 3/6/2009 Removed commercial temperature package. © 2009 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. ...