78Q8430-100CGTR/F Maxim Integrated Products, 78Q8430-100CGTR/F Datasheet - Page 72

• Manufacturer Part Number: 78Q8430-100CGTR/F
• Description: Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
• Manufacturer: Maxim Integrated Products

78Q8430 Data Sheet
7.6.38 Transmit RMON Mask Register
7.6.39 Receive RMON Interrupt Register
Note: All bits are cleared on read.
7.6.40 Receive RMON Mask Register
7.6.41 Host Interrupt Register
72
Name: TRMR
Bits
31:0
Name: RRIR
Bits
31:0
Name: RRMR
Bits
31:0
Name: HIR
Bits
31:21
20
19
18
17
16
15:13
12
11
10:9
8
7
Type
Type
Type
Type
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
X
X
X
Default
Default
Default
Default
0x0000
0x0000
0x0000
0x000
0000
0000
0000
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
0
0
0
0
0
0
0
0
0
0
Description
Tx RMON Interrupt Mask
When a bit is set, it enables the Tx RMON interrupt for the
corresponding bit in the TRIR. When a bit is clear, the corresponding
bit in the TRIR will still be set on its event and cleared on read but will
not be passed on to the HIR.
Description
RMON Rx Counter Rollover
Set when the RMON Rx counter with an index equal to the bit number
plus 32 has rolled over.
Description
Rx RMON Interrupt Mask
When a bit is set, it enables the Rx RMON interrupt for the
corresponding bit in the RRIR. When a bit is clear, the corresponding
bit in the RRIR will still be set on its event and cleared on read but will
not be passed on to the HIR.
Description
Reserved
WAKE
PME is asserted low (a power event has occurred).
QUE Status
QSIR interrupt.
QUE Overflow/Underrun
OUIR interrupt.
PHY
RMON
Reserved
Tx Bad
A transmitted frame had an error.
Rx Bad
A frame was received with an error.
Reserved
Late Rx Notify
This interrupt is asserted each time an entire frame is added to the
receive QUE.
Early Rx Notify
Data reception has started (delayed by the IDCR).
Block: CTL
Block: CTL
Block: CTL
Block: CTL
Address: 0x1D4
Address: 0x1D8
Address: 0x1DC
Address: 0x1E8
DS_8430_001
Rev. 1.2