78Q8430-100CGTR/F Maxim Integrated Products, 78Q8430-100CGTR/F Datasheet - Page 73

• Manufacturer Part Number: 78Q8430-100CGTR/F
• Description: Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
• Manufacturer: Maxim Integrated Products

DS_8430_001
Note: Bits 15:0 are cleared on read. Bits 31:16 are only cleared when the source is cleared.
7.6.42 Host Interrupt Mask Register
Rev. 1.2
Name: HIR
Bits
6
5
4
3
2
1
0
Name: HIMR
Bits
31:0
Type
Type
RW
RO
RO
RO
RO
RO
RO
RO
Default
Default
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
0
0
0
0
0
0
0
Description
Reserved.
Late Tx Notify
Interrupt on completion. (See PCWR)
Early Tx Notify
Interrupt at the start of transmission. (See PCWR)
WATER MARK
Interrupt when the free BLOCK count hits the low water mark.
QUE Overflow
Interrupt when a QUE requests memory and there is none.
PAUSE
Interrupt when the local pause changes state (on/off).
Class
Packet classification interrupt.
Description
Host Interrupt Mask
When a bit is set here it enables the host interrupt for the corresponding
bit in the HIR. When a bit is clear here, the corresponding bit in the HIR
will still be set on its event and cleared on read but will not trigger an
interrupt on INT.
Block: CTL
Block: CTL
Address: 0x1E8
Address: 0x1EC
78Q8430 Data Sheet
73