78Q8430-100CGTR/F Maxim Integrated Products, 78Q8430-100CGTR/F Datasheet - Page 77

• Manufacturer Part Number: 78Q8430-100CGTR/F
• Description: Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
• Manufacturer: Maxim Integrated Products

DS_8430_001
7.7.4
MR2: PHY Identifier Register 1
MR3: PHY Identifier Register 2
7.7.5
Rev. 1.2
Bits
1
0
Bits
15:0
Bits
15:10
9:4
3:0
Bits
15
14
13
12:5
12
11
10
9
8
PHY Identifier Registers – MR2, MR3
PHY Auto-Negotiation Advertisement Registers – MR4
Symbol
JAB
EXTD
Symbol
NP
RSVD
RF
TAF
A7
ASYMP
PAUSE
A4
A3
Symbol
OUI
[23:6]
Symbol
OUI
[5:0]
MN
RN
Type
RC/LH
R/W
R/W
R/W
R/W
R/W
Type
Type
Type
R
R
R
R
R
R
R
R
R
Default Description
Default Description
000Eh Organizationally Unique Identifier
(0Fh)
Value Description
Value Description
1Ch
23h
03h
0
0
0
0
0
0
0
1
0
1
This value is 00-C0-39 for Teridian Semiconductor Corporation.
This register contains 16 of the upper 18 bits of the identifier.
Organizationally Unique Identifier
The remaining 6 bits of the 24-bit OUI.
Model Number
The 23 from the model number is encoded into the 6 bits.
Revision Number
The value 0011 corresponds to the third revision of the silicon.
Next Page
Not supported. Reads logic zero.
Reserved
Remote Fault
Setting this bit to 1 allows the device to indicate to the link
partner a Remote Fault Condition.
Technology Ability Field
The default value of this field is dependent upon the MR1.15:
11 register bits. This field can be overwritten by management
to auto-negotiate to an alternate common technology. Writing
to this register has no effect until auto-negotiation is re-initiated.
Reserved
Asymmetric PAUSE Operation for Full Duplex Links
0 = Asymmetric PAUSE operation not supported
1 = Asymmetric PAUSE operation is supported
Writing to this register has no effect until auto-negotiation is
re-initiated.
PAUSE Operation for Full Duplex Links
0 = PAUSE operation not supported
1 = PAUSE operation is supported
Writing to this register has no effect until auto-negotiation is
re-initiated.
100BASE-T4
The 78Q8430 PHY does not support 100BASE-T4 operations.
100BASE-TX Full Duplex
This bit will be set to 1 upon reset and is writeable. Writing to
this register has no effect until auto-negotiation is re-initiated.
Jabber Detect
In 10Base-T mode, this bit is set during a jabber event. After
the event, the bit remains set until cleared by a read operation.
Extended Capability
Reads 1 to indicate the 78Q8430 PHY provides an extended
register set (MR2 and beyond).
78Q8430 Data Sheet
77