78Q8430-100CGTR/F Maxim Integrated Products, 78Q8430-100CGTR/F Datasheet - Page 25
78Q8430-100CGTR/F
Manufacturer Part Number
78Q8430-100CGTR/F
Description
Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
Manufacturer
Maxim Integrated Products
Datasheet
1.78Q8430-ARM9-EVM.pdf
(88 pages)
- Current page: 25 of 88
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DS_8430_001
6 Functional Description
6.1
6.1.1
Figure 12 presents an overview of the functional layers of the 78Q8430. On the left side are the signals,
which connect to the GBI bus. On the upper and middle right, the blocks that implement the MAC side of
the MII are shown. These blocks are connected to the embedded PHY. On the lower right, connections
to the EEPROM are shown.
6.1.2
Figure 13 shows the functional blocks of the internal 78Q8430 PHY. The signals shown on the left side
are the internal MII signals to the MAC. These signals are multiplexed with their respective external pins
for use with an external PHY device. The 78Q8430 is not a two-port device. Only one PHY interface can
be operational.
Rev. 1.2
BOOTSZ[1:0]
ENDIAN[1:0]
WAITMODE
BUSMODE
CLKMODE
MEMWAIT
WRB/OEB
BUSCLK
RESETB
TRSTB
TCLK
PMEB
TMS
TDO
ADDR
DATA
INTB
TDI
CSB
Internal Block Diagrams
Internal Digital Block
Internal PHY
Boundary
1149.1
System
Address
JTAG
IEEE
Scan
& Data
Control
EMI
EMI
Bus
QUE Status
Register
4 Queue
Write Logic
1 Queue
Read Logic
Controller
Controller
Snoop
Figure 12: Internal Digital Block Diagram
CTL
Packet Status
Register
TX/RX
Manager
Memory
Memory
Queue
RMON
DMA Status
Register
MAC Status
Read/Write
Register
Classify
Queue
Packet
Logic
CAM
Wake-up
Network
EEPROM/
Control
Control
Flow
ROM
78Q8430 Data Sheet
PROM_CLK
PROM_CS
PROM_DO
Controller
MAC Half
PROM_DI
MAC MII
Transmit
Register
Receive
Duplex
MAC
MII
MII
25
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