78Q8430-100CGTR/F Maxim Integrated Products, 78Q8430-100CGTR/F Datasheet - Page 59

• Manufacturer Part Number: 78Q8430-100CGTR/F
• Description: Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
• Manufacturer: Maxim Integrated Products

DS_8430_001
7.6
7.6.1
7.6.2
7.6.3
Rev. 1.2
Name: DMA
Bits
31:18
17
16
15:10
9:0
Name: RPSR
Bits
31
30
29
28
27
26
25
24
23:16
15:0
Name: TPSR
Bits
31
30
29
CTL Registers
DMA Control and Status Register
Receive Packet Status Register
Transmit Packet Status Register
Type
Type
Type
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
X
X
Default
Default
Default
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
Reset Val: 0x0E00_0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Reserved
Read Mode
Once this bit is set the host interface will be in DMA read mode until the
bit is cleared by a write to this register.
Write Mode
Once this bit is set the host interface will be in DMA write mode until the
bit is cleared by a read to this register.
Reserved
Address
The location of the register to direct DMA access to.
Description
Done
When not set the packet is still in the process of ingressing the QUE.
Length Error
The packet length was not correct.
Truncated
The packet was truncated and is incomplete.
Collision
The packet suffered a collision and is incomplete.
MII Error
Dangling Byte
The received packet length was not an integer number of bytes.
CRC
Ethernet CRC checksum error.
Checksum
IP Header checksum error.
Classification
The packet classification results.
Count
The total number of bytes currently in the QUE for this packet. When
the Done bit is set, this represents the actual packet size.
Description
Done
When not set, the frame is still in transmission. When set, the content is
egressing the QUE.
Halted
The packet was halted.
Truncated
The packet was truncated and is incomplete.
Block: CTL
Block: CTL
Block: CTL
Address: 0x100
Address: 0x104
Address: 0x108
78Q8430 Data Sheet
59