CS5360-KS Cirrus Logic Inc, CS5360-KS Datasheet - Page 12
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CS5360-KS
Manufacturer Part Number
CS5360-KS
Description
IC, ADC, 24BIT, 50KSPS, SSOP-20
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS5360-KS.pdf
(22 pages)
Specifications of CS5360-KS
Resolution (bits)
24bit
Sampling Rate
50kSPS
Input Channel Type
Differential
Data Interface
Serial
Supply Voltage Range - Analog
4.75V To 5.25V
Supply Voltage Range - Digital
4.75V To 5.25V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5360-KS
Manufacturer:
CRYSTAL
Quantity:
20 000
Company:
Part Number:
CS5360-KSR
Manufacturer:
MISCELLANEOUS
Quantity:
67 000
Part Number:
CS5360-KSZ
Manufacturer:
CIRRUS
Quantity:
20 000
taken high during normal operation, the current
value of the dc offset register is frozen and this dc
offset will continue to be subtracted from the con-
version result. This feature makes it possible to per-
form a system calibration by:
1) removing the signal source (or grounding the
2) running the CS5360 with the HP DEFEAT pin
3) taking the HP DEFEAT pin high, disabling the
A system calibration performed in this way will
eliminate offsets anywhere in the signal path be-
tween the calibration point and the CS5360.
The characteristics of the first-order high pass filter
are outlined below for an output sample rate of
48 kHz. This filter response scales linearly with
sample rate.
Frequency response: -3 dB @ 0.9 Hz
Phase deviation:
Passband ripple:
4. INPUT LEVEL MONITORING
The CS5360 includes independent Peak Input Lev-
el Monitoring for each channel. The analog-to-dig-
ital converter continually monitors the peak digital
signal for both channels, prior to the digital limiter,
and records these values in the Active registers.
This information can be transferred to the Output
registers by a high to low transition on the Peak Up-
date pin (PU) which will also reset the Active reg-
ister. The Active register contains the peak signal
level since the previous peak update request.
The 8-bit contents of the output registers are avail-
able in all interface modes and are present in the
data block as shown in Figure 7. The monitoring
12
input signal) at the input to the subsystem con-
taining the CS5360,
low (high pass filter enabled) until the filter set-
tles (approximately 1 second), and
high pass filter and freezing the stored dc off-
set.
-0.01 dB @ 20 Hz
2.6 degrees @ 20 Hz
None
function can be formatted to indicate either High
Resolution Mode or Bar Graph Mode. The moni-
toring function is determined on power-up by the
presence of a 47 k
FRAME. The addition of a 47 k pull-down resis-
tor on the FRAME pin sets the monitoring function
to the Bar Graph mode.
4.1
Bits P7-P0 indicate the peak input level since the
previous peak update (or low transition on the Peak
Update pin). If the full scale input level is exceeded
(Bit P7 high), bits P5-P0 represent the peak value
up to 3 dB above full-scale in 1 dB steps. If the
ADC input level is less than full-scale, bits P5-P0
represent the peak value from -60 dB to 0 dB of full
scale in 1 dB steps. The PSL outputs are accurate to
within 0.25 dB. Bit P6 provides a coarse means of
determining an ADC input idle condition. Bit P7
indicates an ADC overflow condition, if the ADC
input level is greater than full-scale.
P7 - Overrange
0 - Analog input less than full-scale level
1 - Analog input greater than full-scale
P6 - Idle channel
0 - Analog input >-60 dB from full-scale
1 - Analog input <-60 dB from full-scale
P5 to P0 - Peak Signal Level Bits (1 dB steps)
0 dB
-1 dB
-2 dB
-60 dB
0 dB
+1 dB
+2 dB
+3 dB
Table 3. Peak Signal Level Bits - High Resolution Mode
High Resolution Mode
Inputs <0 dB
Inputs >0 dB
pull-down resistor on
000000
000001
000010
P5 - P0
P5 - P0
000000
000001
000010
111100
000011
CS5360
DS280PP2