CS5360-KS Cirrus Logic Inc, CS5360-KS Datasheet - Page 2
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CS5360-KS
Manufacturer Part Number
CS5360-KS
Description
IC, ADC, 24BIT, 50KSPS, SSOP-20
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS5360-KS.pdf
(22 pages)
Specifications of CS5360-KS
Resolution (bits)
24bit
Sampling Rate
50kSPS
Input Channel Type
Differential
Data Interface
Serial
Supply Voltage Range - Analog
4.75V To 5.25V
Supply Voltage Range - Digital
4.75V To 5.25V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5360-KS
Manufacturer:
CRYSTAL
Quantity:
20 000
Company:
Part Number:
CS5360-KSR
Manufacturer:
MISCELLANEOUS
Quantity:
67 000
Part Number:
CS5360-KSZ
Manufacturer:
CIRRUS
Quantity:
20 000
TABLE OF CONTENTS
LIST OF FIGURES
2
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 3
2. SYSTEM DESIGN ..................................................................................................................... 8
3. SERIAL DATA INTERFACE ..................................................................................................... 8
4. INPUT LEVEL MONITORING ................................................................................................. 11
5. PIN DESCRIPTIONS .............................................................................................................. 15
6. PARAMETER DEFINITIONS .................................................................................................. 18
7. PACKAGE DIMENSIONS ....................................................................................................... 19
Figure 1. SCLK to SDATA & LRCK - MASTER Mode Format 0 and 1 ........................................... 6
Figure 3. SCLK to LRCK & SDATA - SLAVE Mode Format 0 & 1 .................................................. 6
Figure 2. SCLK to SDATA & LRCK - MASTER Mode Format 2 ..................................................... 6
Figure 4. SCLK to LRCK & SDATA - SLAVE Mode Format 2......................................................... 6
Figure 5. SCLK to Frame Delay ...................................................................................................... 6
ANALOG CHARACTERISTICS ................................................................................................ 3
DIGITAL FILTER CHARACTERISTICS.................................................................................... 4
DIGITAL CHARACTERISTICS ................................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
SWITCHING CHARACTERISTICS .......................................................................................... 5
2.1 Master Clock ...................................................................................................................... 8
3.1 Serial Data ......................................................................................................................... 8
3.2 Serial Clock ........................................................................................................................ 8
3.3 Left / Right Clock .............................................................................................................. 10
3.4 Master Mode .................................................................................................................... 10
3.5 Slave Mode ...................................................................................................................... 10
3.6 Analog Connections ......................................................................................................... 10
3.7 High Pass Filter ................................................................................................................ 10
4.1 High Resolution Mode ...................................................................................................... 11
4.2 Bar Graph Mode .............................................................................................................. 12
4.3 Overflow ........................................................................................................................... 12
4.4 Initialization ...................................................................................................................... 12
4.5 Initialization with High Pass Filter Enabled ...................................................................... 12
4.6 Initialization and Internal Calibration with High Pass Filter Disabled ............................... 12
4.7 Power-Down .................................................................................................................... 13
4.8 Grounding and Power Supply Decoupling ....................................................................... 13
4.9 Digital Filter ...................................................................................................................... 13
CS5360
DS280PP2