CS4396-KSZ Cirrus Logic Inc, CS4396-KSZ Datasheet - Page 15

• Manufacturer Part Number: CS4396-KSZ
• Description: IC, DAC, 24BIT, 192KSPS, SOIC-28
• Manufacturer: Cirrus Logic Inc

Specifications of CS4396-KSZ

• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 20mA
• Digital Ic Case Style: SOIC
• Data Interface: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Clock - SCLK
Left/Right Clock - LRCK
Serial Audio Data - SDATA
Soft Mute - MUTE
DS288PP1
Sample Rate
Sample Rate
Sample Rate
176.4
(kHz)
(kHz)
(kHz)
Pin 11, Input
Function:
Pin 12, Input
Function:
Pin 13, Input
Function:
Pin 15, Input
Function:
44.1
88.2
192
32
48
64
96
Table 5. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies
Table 6. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock Frequencies
Clocks individual bits of serial data into the SDATA pin. The required relationship between the Left/Right
clock, serial clock and serial data is defined by either the Mode Control Byte in Control Port Mode or the
M0 - M4 pins in Hardware Mode. The options are detailed in Figures 20-23
The Left/Right clock determines which channel is currently being input on the serial audio data input,
SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in
Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas
Right/Left pairs will exhibit a one sample period difference. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-
tailed in Figures 20-23
Two’s complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial
clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-
tailed inin Figures 20-23
The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cy-
12.2880
12.2880
12.2880
11.2896
11.2896
11.2896
8.1920
8.1920
256x
128x
64x
12.2880
16.9344
18.4320
12.2880
16.9344
18.4320
16.9344
18.4320
384x
192x
96x
MCLK (MHz)
MCLK (MHz)
MCLK (MHz)
16.3840
22.5792
24.5760
16.3840
22.5792
24.5760
22.5792
24.5760
512x
256x
128x
24.5760
33.8688
36.8640
24.5760
33.8688
36.8640
33.8688
36.8640
768x
384x
192x
CS4396
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