CS4382-KQZ Cirrus Logic Inc, CS4382-KQZ Datasheet
CS4382-KQZ
Specifications of CS4382-KQZ
Available stocks
Related parts for CS4382-KQZ
CS4382-KQZ Summary of contents
Page 1
... The CS4382 is available in a 48-pin LQFP package in Commercial grade (-10°C to +70°C). The CDB4382 Customer Demonstration Board is also available for de- vice evaluation and implementation suggestions. ...
Page 2
... Volume Control (Addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh, 10h, 11h) ...................................... 23 4.7.1 Mute (MUTE) ................................................................................................................... 23 4.7.2 Volume Control (xx_VOL) ................................................................................................ 23 4.8 Chip Revision (Address 12h) ....................................................................................................... 24 4.8.1 Part Number ID (PART) [Read Only] ............................................................................... 24 5. PIN DESCRIPTION .............................................................................................................................. 25 6. APPLICATIONS .................................................................................................................................. 28 6.1 Grounding and Power Supply Decoupling .................................................................................... 28 2 ® FORMAT ........................................... 11 ............................................................................................... 13 CS4382 DS514F2 ...
Page 3
... Figure 20. Double-Speed (fast) Passband Ripple...................................................................................... 34 Figure 21. Double-Speed (slow) Stopband Rejection ................................................................................ 35 Figure 22. Double-Speed (slow) Transition Band ...................................................................................... 35 Figure 23. Double-Speed (slow) Transition Band (detail) .......................................................................... 35 Figure 24. Double-Speed (slow) Passband Ripple .................................................................................... 35 Figure 25. Quad-Speed (fast) Stopband Rejection .................................................................................... 35 Figure 26. Quad-Speed (fast) Transition Band .......................................................................................... 35 Figure 27. Quad-Speed (fast) Transition Band (detail) .............................................................................. 36 DS514F2 ..................................................................................................................... 37 CS4382 3 ...
Page 4
... Table 2. Digital Interface Formats - DSD Mode ......................................................................................... 18 Table 3. ATAPI Decode ............................................................................................................................. 22 Table 4. Example Digital Volume Settings ................................................................................................. 23 Table 5. Common Clock Frequencies........................................................................................................ 27 Table 6. Digital Interface Format, Stand-Alone Mode Options................................................................... 27 Table 7. Mode Selection, Stand-Alone Mode Options ............................................................................... 27 Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................................ 27 4 CS4382 DS514F2 ...
Page 5
... For Double-Speed Mode kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz; For Quad-Speed Mode 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz; For Direct Stream Digital Mode 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz). Parameters CS4382-KQZ Dynamic Performance - All PCM modes and DSD Specified Temperature Range Dynamic Range (Note 2) ...
Page 6
... I LS VLS (Note 8) (Note 5) normal operation power-down (Note 8) normal operation power-down (Note 8) θ multi-layer JA θ dual-layer JA θ kHz) PSRR (60 Hz) and includes attenuation due CS4382 Typ Max Units 91% V 96% V Vpp VDC A μ 0.1 - 100 - ppm/°C 100 - - - kΩ - 100 ...
Page 7
... Fs = 44.1 kHz - - kHz - - -0.01 - .583 - (Note 13 4.6/ kHz - - ±0.03/ -0.01 - .635 - (Note 13 4.7/ kHz - - ±0.01/ CS4382 Slow Roll-Off (Note 10) Max Min Typ Max (Note 11) .454 0 - 0.417 .499 0 - 0.499 +0.01 -0.01 - +0.01 - .583 - - - 6.5/ ±0.14/Fs ±0. ±0.23 ±0. ±0.14 ±0. ±0.09 (Note 11) ...
Page 8
... VLS+ 0.4 -0.3 VLC+ 0.4 -55 125 A -65 150 Min Typ Max 4.5 5.0 5.5 3.0 3.3 5.5 1.8 5.0 5.5 1.8 5.0 5.5 CS4382 Units μ Units °C °C Units DS514F2 ...
Page 9
... Quad-Speed Mode Fs t sclkl t sclkh t sclkw t sclkw (Note 16) t slrd t slrs t sdlrs t sdh (Note 17) for suggested MCLK frequencies. LRCK t slrs t slrd t sclkl SCLK t sdlrs Figure 1. Serial Mode Input Timing CS4382 = 30 pF) L Min Typ Max 1.024 - 51.2 6.400 - 51.2 6.400 - 51 100 100 - 200 ...
Page 10
... DSD_L, DSD_R Figure 2. Direct Stream Digital - Serial Audio Input Timing 10 Symbol Min (Note 18) 4.096 (All DSD t sclkl t sclkh (64x Oversam- 1.024 (128x Oversampled) 2.048 t sdlrs t sdh t sclkl t t sdlrs sdh CS4382 = 30 pF) L Typ Max Unit - 38.4 MHz 3.2 MHz - 6.4 MHz ...
Page 11
... Double-Speed Mode, × 128 Fs DATA R/W ACK 1-8 Figure 3. Control Port Timing - I²C Format CS4382 ® FORMAT = 30 pF) L Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 300 fc 4.7 ...
Page 12
... Figure 4. Control Port Timing - SPI Format CS4382 ™ FORMAT = 30 pF) L Min Max Unit MCLK ---------------- - - MHz 2 500 - ns 500 - ns 1.0 - µ ---------------- - - ns MCLK 1 ---------------- - - ns MCLK ...
Page 13
... D ig ita µ tro lle µ tro tio n Figure 5. Typical Connection Diagram Control Port DS514F2 0 .1 µ CS4382 + µ µ itio tin itio tin itio tin itio tin itio tin itio tin itio tin itio tin rive µ µ µ µ ...
Page 14
... Figure 6. Typical Connection Diagram Stand-Alone µ CS4382 + µ µ itio tin itio tin riv itio tin itio tin itio tin itio tin itio tin itio tin riv µ µ µ µ tio tie tic fig u ra tio DS514F2 ...
Page 15
... P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 A3_VOL6 A3_VOL5 A3_VOL4 B3_VOL6 B3_VOL5 B3_VOL4 P4ATAPI4 P4ATAPI3 P4ATAPI2 P4ATAPI1 A4_VOL6 A4_VOL5 A4_VOL4 B4_VOL6 B4_VOL5 B4_VOL4 PART2 PART1 PART0 CS4382 AMUTE Reserved Reserved DEM1 DEM0 INV_B2 INV_A2 INV_B1 P1ATAPI0 P1FM1 A1_VOL3 A1_VOL2 A1_VOL1 B1_VOL3 B1_VOL2 B1_VOL1 P2ATAPI0 ...
Page 16
... When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate the possibility of audible artifacts DAC4_DIS DAC3_DIS CS4382 DAC2_DIS DAC1_DIS PDN DS514F2 ...
Page 17
... Table 1. Digital Interface Formats - PCM Mode DS514F2 DIF0 SDIN4CLK DESCRIPTION Left Justified 24-bit data I² 24-bit data Right Justified, 16-bit data Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 18-bit data Reserved Reserved CS4382 2 1 SDIN3CLK SDIN2CLK SDIN1CLK 0 0 Figures 33-38. Format FIGURE ...
Page 18
... DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate RMP_UP Reserved CS4382 Note * * * * * * AMUTE ...
Page 19
... When set to 1 the MUTEC pin(s) are low when active. Note: When the onboard mute circuitry is designed for active low, the MUTEC outputs will be high (un- muted) for the period of time during reset and before this bit is enabled to 1. DS514F2 CS4382 19 ...
Page 20
... This Function allows the user to select whether the interpolation filter has a fast or slow roll off. For filter characteristics please see Section 1. 4.4.2 De-Emphasis Control (DEM) Default = Disabled 01 - 44.1 kHz kHz kHz Function FILT_SEL Reserved CS4382 Section 5. Pin DEM1 DEM0 RMP_DN DS514F2 ...
Page 21
... Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are deter- mined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled. DS514F2 Figure 39 INV_A3 INV_B2 PxATAPI2 PxATAPI1 CS4382 INV_A2 INV_B1 INV_A1 PxATAPI0 PxFM1 PxFM0 ...
Page 22
... ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4382 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table ATAPI4 ATAPI3 ATAPI2 and Figure ATAPI1 ATAPI0 ...
Page 23
... Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent to enabling the MUTE bit. Binary Code 0000000 0010100 0101000 0111100 1011010 Table 4. Example Digital Volume Settings DS514F2 xx_VOL4 xx_VOL3 Decimal Value Volume Setting - - - -90 dB CS4382 xx_VOL2 xx_VOL1 xx_VOL0 Table 4. The volume changes are imple- 23 ...
Page 24
... Chip Revision (Address 12h PART3 PART2 PART1 1 0 4.8.1 Part Number ID (PART) [Read Only] 1010 - CS4382 Function: This read-only register can be used to identify the model number of the device PART0 Reserved CS4382 Reserved Reserved Reserved - - - DS514F2 ...
Page 25
... DC current is less than the maximum specified in the Analog Characteristics and Specifications sec- tion. DS514F2 DSDA2 1 DSDB1 2 DSDA1 GND MCLK 6 CS4382 7 SDIN1 8 SCLK1 9 LRCK2 10 SDIN2 11 12 SCLK2 Pin Description CS4382 36 AOUTA2- 35 AOUTA2+ 34 AOUTB2+ 33 AOUTB2 GND 30 AOUTA3- AOUTA3 AOUTB3+ 27 AOUTB3- 26 AOUTA4- 25 AOUTA4+ Table 5 illustrates 25 ...
Page 26
... Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. DSDA3 47 DSDB3 46 DSDA4 45 DSDB4 44 26 Pin Description I²C Mode as shown in the Typical Connection Diagram. I² Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in CS4382 I²C Mode and requires an external pull-up I²C Mode; 6 and 7. DS514F2 ...
Page 27
... DSD data with a 4x MCLK to DSD data rate 1 Reserved 0 Reserved 1 Reserved 0 128x oversampled DSD data with a 2x MCLK to DSD data rate 1 Reserved 0 Reserved 1 Reserved CS4382 Control port only modes 512x 768x* 1024x* 16.3840 24.5760 32.7680 22.5792 33.8688 45.1584 24.5760 36.8640 49.1520 ...
Page 28
... PCM Mode Select The CS4382 operates in one of three PCM oversampling modes based on the input sample rate. Mode se- lection is determined by the M3 and M2 pins in Stand-Alone Mode or the FM bits in Control Port Mode. Sin- gle-Speed Mode supports input sample rates kHz and uses a 128x oversampling ratio. Double- Speed Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x ...
Page 29
... The CS4382 has MAP auto increment capability, enabled by the INCR bit in the MAP register, which is the MSB. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written from register 01h to 08h and then from 09h and 11h, allowing block reads or writes of suc- cessive registers in two separate sections (the counter will not auto-increment to register 09h from register 08h) ...
Page 30
... The control port has 2 formats: SPI and I²C, with the CS4382 operating as a slave device. If I²C operation is desired, AD0/CS should be tied to VLC or GND. If the CS4382 ever detects a high to low transition on AD0/CS after power-up and after the control port is activated, SPI format will be selected. ...
Page 31
... When Auto Map Increment is enabled, the register must be written it two separate blocks: from register 01h to 08h and then from 09h and 11h. The counter will not auto-increment to register 09h from register 08h DS514F2 Figure 7. Control Port Timing, I²C Format Figure 8. Control Port Timing, SPI Format MAP4 MAP3 CS4382 MAP2 MAP1 MAP0 ...
Page 32
... MAP4-0 (Memory Address Pointer) Default = ‘00000’ 32 CS4382 DS514F2 ...
Page 33
... Figure 12. Single-Speed (fast) Passband Ripple 100 120 0.8 0.9 1 0.4 0.42 Figure 14. Single-Speed (slow) Transition Band CS4382 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) ...
Page 34
... Figure 18. Double-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 20. Double-Speed (fast) Passband Ripple CS4382 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 ...
Page 35
... Figure 24. Double-Speed (slow) Passband Ripple 100 120 0.7 0.8 0.9 1 0.2 Figure 26. Quad-Speed (fast) Transition Band CS4382 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0 ...
Page 36
... Figure 30. Quad-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.02 Figure 32. Quad-Speed (slow) Passband Ripple CS4382 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.04 0.06 0.08 ...
Page 37
... Figure 35. Format 2 - Right Justified 16-bit Data LRCK Left Channel SCLK SDINx clocks Figure 36. Format 3 - Right Justified 24-bit Data DS514F2 + LSB MSB + LSB MSB Figure 34. Format 1 - I² 24-bit Data CS4382 Right Channel + LSB Right Channel + LSB Right Channel Right Channel ...
Page 38
... Figure 38. Format 5 - Right Justified 18-bit Data -10dB L SDINx R Figure 40. Channel Pair Routing Diagram (x = Channel Pair Gain dB T1=50 µs 0dB F1 F2 3.183 kHz 10.61 kHz Figure 39. De-Emphasis Curve Channel Pair x Control CS4382 Right Channel Right Channel µs Frequency AOUTAx+ DAC AOUTAx- AOUTBx+ DAC AOUTBx- DS514F2 ...
Page 39
... Left Chan nel Audio D ata SDINx Right Chan nel Audio D ata Figure 41. ATAPI Block Diagram (x = channel pair DS514F2 A Channel Volume Control Σ B Channel Volume Control Figure 42. Recommended Output Filter CS4382 MUTE Aout Ax Σ MUTE AoutBx 39 ...
Page 40
... Convention of the Audio Engineering Society, October 1992. 2. CDB4382 Evaluation Board Datasheet 3. Design Notes for a 2-Pole Filter with Differential Input by Steven Green. Cirrus Logic Application Note AN48, available at http:www.cirrus.com 4. The I²C-Bus Specification: Version 2.0 Philips Semiconductors, December 1998. http://www.semiconductors.philips.com 40 CS4382 DS514F2 ...
Page 41
... Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS022 CS4382 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9 ...
Page 42
... I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. 42 Grade Temp Range 48-pin YES Commercial -10°C to +70°C LQFP - - Changes Section 4.1.4 Section 4.2.1 Section 6.2 “Power and Thermal Characteristics” on page 6 www.cirrus.com. CS4382 Container Order # Tray CS4382-KQZ Tape and Reel CS4382-KQZR - - CDB4382 DS514F2 ...