DS92LV1212AMSA National Semiconductor, DS92LV1212AMSA Datasheet - Page 11

• Manufacturer Part Number: DS92LV1212AMSA
• Description: IC, DESERIALIZER, 40MHZ, 10BIT, SSOP-28
• Manufacturer: National Semiconductor

Specifications of DS92LV1212AMSA

• Serdes Function: Deserializer
• Data Rate: 400Mbps
• Ic Output Type: LVTTL
• No. Of Inputs: 1
• No. Of Outputs: 10
• Supply Voltage Range: 3V To 3.6V
• Driver Case Style: SSOP
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Information
the receiver end. Please note that in point-to-point configu-
ration, the potential of offsetting the ground levels of the
Serializer vs. the Deserializer must be considered. Also, Bus
LVDS provides a +/− 1.2V common mode range at the
receiver inputs.
Failsafe Biasing for the DS92LV1212A
The DS92LV1212A has an improved input threshold sensi-
tivity of +/− 50mV versus +/− 100mV for the DS92LV1210 or
DS92LV1212. This allows for greater differential noise mar-
gin in the DS92LV1212A. However, in cases where the
receiver input is not being actively driven, the increased
sensitivity of the DS92LV1212A can pickup noise as a signal
and cause unintentional locking . For example, this can
occur when the input cable is disconnected.
External resistors can be added to the receiver circuit board
to prevent noise pick-up. Typically, the non-inverting receiver
input is pulled up and the inverting receiver input is pulled
down by high value resistors. the pull-up and pull-down
resistors (R
termination resistor (R
when they are not connected to an active driver. The value of
the pull-up and pull-down resistors should be chosen so that
enough current is drawn to provide a +15mV drop across the
termination resistor. Please see Figure 11 for the Failsafe
Biasing Setup.
The DS92LV1212A can be “Hot Inserted” into operating serial busses without interrupting bus communication. The random lock feature allows the
DS92LV1212A to synchronize to the bus traffic and receive data.
1
and R
2
) provide a current path through the
L
) which biases the receiver inputs
FIGURE 10. Random Lock Allows Hot Insertion into Serial Busses
(Continued)
FIGURE 11. Failsafe Biasing Setup
11
Using t
The parameters t
eye pattern mask to validate signal quality in an actual
application or in simulation.
The parameter t
place data bits in the ideal position to be sampled by the
receiver. The typical t
the crossing point of the Tx data is 80pS ahead of the ideal
crossing point. The t
specify the earliest and latest, repectively, time that a cross-
ing will occur relative to the ideal position.
The parameter t
much of the ideal bit the receiver needs to ensure correct
sampling. After determining this amount, what remains of the
ideal bit that is available for external sources of noise is
called t
mask within the eye opening.
The vertical limits of the mask are determined by the
DS92LV1212A receiver input threshold of +/− 50mV.
Please refer to the eye mask pattern of Figure 12 for a
graphic representation of t
RNM
DJIT
. It is the offset from t
and t
DS101387-26
DS101387-27
RNM
DJIT
DJIT
RNM
DJIT
and t
measures the transmitter’s ability to
is calculated by first measuring how
to Validate Signal Quality
DJIT(min)
parameter of −80pS indicates that
DJIT
RNM
and t
can be used to generate an
and t
DJIT(min or max)
RNM
DJIT(max)
.
parameters
www.national.com
for the test