ISL34321INZ Intersil, ISL34321INZ Datasheet - Page 6

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ISL34321INZ

Manufacturer Part Number
ISL34321INZ
Description
Transceiver IC
Manufacturer
Intersil
Datasheet

Specifications of ISL34321INZ

Serdes Function
Transmitter / Receiver
No. Of Inputs
16
No. Of Outputs
16
Supply Voltage Range
1.7V To 1.9V, 3V To 3.6V
Driver Case Style
TQFP
No. Of Pins
48
Frequency
45MHz
Interface
I2C
Termination Type
SMD
Filter Terminals
SMD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL34321INZ
Manufacturer:
Intersil
Quantity:
10 000
Part Number:
ISL34321INZ
Manufacturer:
INTERSIL
Quantity:
20 000
Part Number:
ISL34321INZ-T13
Manufacturer:
Intersil
Quantity:
10 000
Electrical Specifications
Output Rise and Fall Times
SERIALIZER PARALLEL INTERFACE
PCLK_IN Frequency
PCLK_IN Duty Cycle
Parallel Input Setup Time
Parallel Input Hold Time
DESERIALIZER PARALLEL INTERFACE
PCLK_OUT Frequency
PCLK_OUT Duty Cycle
PCLK_OUT Period Jitter (rms)
PCLK_OUT Spread Width
PCLK_OUT to Parallel Data Outputs
(includes Sync and DE pins)
Deserializer Output Latency
DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN)
REF_CLK Lock Time
REF_CLK to PCLK_OUT Maximum
Frequency Offset
HIGH-SPEED TRANSMITTER
HS Differential Output Voltage,
Transition Bit
HS Differential Output Voltage, Non-
Transition Bit
HS Generated Output Common Mode
Voltage
HS Common Mode Serializer-
Deserializer Voltage Difference
HS Differential Output Impedance
HS Output Latency
HS Output Rise and Fall Times
HS Differential Skew
HS Output Random Jitter
HS Output Deterministic Jitter
PARAMETER
6
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V
VDD_TX = VDD_P = VDD_AN = 3.3V, T
AC-coupling capacitor = 27nF. (Continued)
SYMBOL
VOD
t
t
VOD
t
OR
OSPRD
V
ΔV
R
t
f
t
t
SKEW
t
t
t
ODC
t
OUT
t
CPD
R/
t
f
IDC
t
t
OCM
LPD
t
PLL
OUT
DV
OJ
IN
IS
IH
RJ
DJ
/t
CM
NTR
t
TR
OF
F
Slew rate control set to min
C
Slew rate control set to
max, C
Clock randomizer off
Clock randomizer on
Relative to PCLK_OUT,
(Note 9)
Inherent in the design
PCLK_OUT is the
recovered clock
TXCN = 0x00
TXCN = 0x0F
TXCN = 0xF0
TXCN = 0xFF
TXCN = 0x00
TXCN = 0x0F
TXCN = 0xF0
TXCN = 0xFF
Inherent in the design
20% to 80%
PCLK_IN = 45MHz
PCLK_IN = 45MHz
L
ISL34321
= 8pF
CONDITIONS
L
= 8pF
A
= +25°C, Ref_Res = 3.16kΩ, High-speed
1500
MIN
-1.0
650
650
3.5
1.0
40
80
6
6
4
4
5000
1100
1300
2.35
TYP
±20
<10
100
800
900
800
900
430
600
100
150
0.5
50
50
10
25
1
4
9
7
6
MAX
900
900
120
5.5
45
60
45
14
20
10
September 23, 2010
%t
%t
UNITS
FN6870.1
mV
mV
mV
mV
mV
mV
mV
mV
ps
ps
PCLK
PCLK
MHz
MHz
ppm
mV
ns
ns
%
ns
ns
%
ns
µs
ps
ps
,
PCLK
PCLK
Ω
V
rms
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P

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