DSPIC30F3014-20I/PT Microchip Technology, DSPIC30F3014-20I/PT Datasheet - Page 60

• Manufacturer Part Number: DSPIC30F3014-20I/PT
• Description: IC, DSC, 16BIT, 24KB 40MHZ, 5.5V, TQFP44
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F3014-20I/PT

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F301420IPT

dsPIC30F3014/4013
8.1
The user-assignable interrupt priority (IP<2:0>) bits for
each individual interrupt source are located in the
3 LSbs of each nibble within the IPCx register(s). Bit 3
of each nibble is not used and is read as a ‘0’. These
bits define the priority level assigned to a particular
interrupt by the user.
Since more than one interrupt request source may be
assigned to a specific user-assigned priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority” and is
final.
Natural Order Priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
Table 8-1
corresponding interrupt sources and associated vector
numbers for the dsPIC30F3014 and dsPIC30F4013
devices, respectively.
The ability for the user to assign every interrupt to one
of seven priority levels means that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PLVD (Pro-
grammable Low-Voltage Detect) can be given a priority
of 7. The INT0 (External Interrupt 0) may be assigned
to priority Level 1, thus giving it a very low effective
priority.
DS70138G-page 60
Note:
Note 1: The natural order priority scheme has 0
2: The natural order priority number is the
Interrupt Priority
and
The user-assignable priority levels start at
0 as the lowest priority and Level 7 as the
highest priority.
as the highest priority and 53 as the
lowest priority.
same as the INT number.
Table 8-2
list the interrupt numbers,
TABLE 8-1:
Number
17-22
28-41
43-53
INT
10
12
13
14
15
16
23
24
25
26
27
42
11
0
1
2
3
4
5
6
7
8
9
Number
Vector
Highest Natural Order Priority
25-30
36-49
51-61
Lowest Natural Order Priority
10
12
13
14
15
16
17
18
19
20
21
22
23
24
31
32
33
34
35
50
11
8
9
dsPIC30F3014 INTERRUPT
VECTOR TABLE
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1
T1 – Timer1
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer2
T3 – Timer3
SPI1
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC – ADC Convert Done
NVM – NVM Write Complete
SI2C – I
MI2C – I
Input Change Interrupt
INT1 – External Interrupt 1
Reserved
INT2 – External Interrupt 2
U2RX – UART2 Receiver
U2TX – UART2 Transmitter
Reserved
C1 – Combined IRQ for CAN1
Reserved
LVD – Low-Voltage Detect
Reserved
 2010 Microchip Technology Inc.
Interrupt Source
2
2
C™ Slave Interrupt
C Master Interrupt