DSPIC30F4012-20I/SO Microchip Technology, DSPIC30F4012-20I/SO Datasheet
DSPIC30F4012-20I/SO
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DSPIC30F4012-20I/SO Summary of contents
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... MPLAB ICD 2 Ready The errata described in this section will be addressed in future revisions of dsPIC30F4011 dsPIC30F4012 devices. © 2008 Microchip Technology Inc. dsPIC30F4011/4012 Silicon Errata Summary The following list summarizes the errata described in further detail throughout the remainder of this document: 1. MAC Class Instructions with ±4 Address ...
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... SDA and SCL pins, causing a false communication start in a single-master configuration or a bus collision in a multi-master configuration. The following sections describe the errata and work around to these errata, where they may apply. © 2008 Microchip Technology Inc. ® DSC ...
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... BRA L1 ;and exit L0:DAW.b w2 L1: .... © 2008 Microchip Technology Inc. dsPIC30F4011/4012 3. Module: Special Function Registers The I/O Port register values can be changed by writing to the following address locations, which are located in unimplemented memory space. A write to these unimplemented addresses could cause an I/O pin configured as an output to change states ...
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... Result in W4 (3) SR<1:0> bits , Result in W2 (3) SR<1:0> bits (4) SR<15:10> bits CORRECT RESULTS ;Load PSVPAG register ;Enable PSV ;Set up W1 for ;indirect PSV access ;from 0x000200 ;works ok ;Load W2 with data ;from program memory ;Carry flag and W4 ;results are ok! © 2008 Microchip Technology Inc. ...
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... Note: For details on the functionality of EDT bit, see section 2.9.2.4 in the dsPIC30F Family Reference Manual. © 2008 Microchip Technology Inc. dsPIC30F4011/4012 6. Module: 4x PLL Operation When the 4x PLL mode of operation is selected, the specified input frequency range of 4-10 MHz is not fully supported. ...
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... One may use a large DISI value and then set the DISICNT register to zero, as shown in Example 6. A macro may also be used to perform this task, as shown in Example 7. // protect CPU IPL modification // set CPU IPL remove DISI protection // safely modify the CPU IPL © 2008 Microchip Technology Inc. ...
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... If the application requires 0% duty cycles, the output compare module can be disabled for 0% duty cycles, and re-enabled for non-zero percent duty cycles. © 2008 Microchip Technology Inc. dsPIC30F4011/4012 10. Module: Output Compare A glitch will be produced on an output compare pin under the following conditions: • ...
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... A/D Channels Configuration REF REF CH X ANx S/H ADC REF REF ANx S/H ADC ANx REF REF REF ANx S/H ADC ANx REF © 2008 Microchip Technology Inc. ...
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... User's code } void __attribute__((__interrupt__)) _QEIInterrupt(void) { IFSxbits.QEIIF = 0; POSCNT_b15 ^= 0x8000; // Overflow or Underflow } © 2008 Microchip Technology Inc. dsPIC30F4011/4012 Work around To prevent this condition from occurring, set MAXCNT to 0x7FFF, which will cause an interrupt to be generated by the QEI module. In addition, a global variable could be used to keep ...
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... Sleep mode. Example 9 described above would apply to a dsPIC30F4011 device. ; Ensure flag is reset ; Return from Interrupt Service Routine the function call would be following the or _GotoSleep demonstrates the work around © 2008 Microchip Technology Inc. ...
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... Note: The above work around is recommended for users for whom application hardware changes are not possible. © 2008 Microchip Technology Inc. dsPIC30F4011/4012 Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz Low-Power (LP) Oscillator with a 64:1 postscaler mode ...
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... Module: Motor Control PWM – PWM Counter Register If the PTDIR bit is set (when PTMR is counting down), and the CPU execution is halted (after a breakpoint is reached), PTMR will start counting PTDIR was zero. Work around None. © 2008 Microchip Technology Inc slave interrupt 2 C nodes receive 2 ...
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... Clock Failure Status bit (OSCCON<3>). If this bit is clear, return from the trap service routine immediately and continue program execution. © 2008 Microchip Technology Inc. dsPIC30F4011/4012 22. Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page ...
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... For example, if the SDA and SCL pins are shared with the UART and SPI pins, and the UART has higher precedence on the port latch pin. DS80215K-page module is that have 2 C © 2008 Microchip Technology Inc. ...
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... Removed silicon issue 11 (Using OSC2/RC15 pin for Digital I/O). Revision K (9/2008) Updated silicon revision to Rev. A2/A3. Replaced 2 issues 16 and with issue 25 (I silicon issues 21 (PLL Lock Status Bit), 22 (PSV 2 Operations) and 23-25 (I C). © 2008 Microchip Technology Inc. dsPIC30F4011/4012 2 C), 19 (Motor 2 C). Added DS80215K-page 15 ...
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... NOTES: DS80215K-page 16 © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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