DSPIC33FJ128MC804-E/ML Microchip Technology, DSPIC33FJ128MC804-E/ML Datasheet - Page 154
![IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN44](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ128MC804-E/ML
Manufacturer Part Number
DSPIC33FJ128MC804-E/ML
Description
IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN44
Manufacturer
Microchip Technology
Series
DsPIC33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ128MC804-E/ML
Core Frequency
40MHz
Core Supply Voltage
3.6V
No. Of I/o's
35
Flash Memory Size
128KB
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +125°C
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b, D/A 6x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 154 of 424
- Download datasheet (6Mb)
REGISTER 9-5:
DS70291D-page 154
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-11
bit 10-8
bit 7
bit 6-0
ASRCSEL
R/W-0
U-0
—
Unimplemented: Read as ‘0’
SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider
1 = Auxiliary Oscillators provides the source clock for Auxiliary Clock Divider
0 = PLL output (F
AOSCMD<1:0>: Auxiliary Oscillator Mode
11 = EC External Clock Mode Select
10 = XT Oscillator Mode Select
01 = HS Oscillator Mode Select
00 = Auxiliary Oscillator Disabled (default)
APSTSCLR<2:0>: Auxiliary Clock Output Divider
111 = divided by 1
110 = divided by 2
101 = divided by 4
100 = divided by 8
011 = divided by 16
010 = divided by 32
001 = divided by 64
000 = divided by 256 (default)
ASRCSEL: Select Reference Clock Source for Auxiliary Clock
1 = Primary Oscillator is the Clock Source
0 = Auxiliary Oscillator is the Clock Source
Unimplemented: Read as ‘0’
U-0
U-0
—
—
ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
SELACLK
VCO
R/W-0
U-0
—
) provides the source clock for the Auxiliary Clock Divider
R/W-0
U-0
Preliminary
—
AOSCMD<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
R/W-0
U-0
—
APSTSCLR<2:0>
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/W-0
U-0
—
R/W-0
U-0
—
bit 8
bit 0
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