DSPIC33FJ128MC804-E/ML Microchip Technology, DSPIC33FJ128MC804-E/ML Datasheet - Page 164
![IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN44](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ128MC804-E/ML
Manufacturer Part Number
DSPIC33FJ128MC804-E/ML
Description
IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN44
Manufacturer
Microchip Technology
Series
DsPIC33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ128MC804-E/ML
Core Frequency
40MHz
Core Supply Voltage
3.6V
No. Of I/o's
35
Flash Memory Size
128KB
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +125°C
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b, D/A 6x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 164 of 424
- Download datasheet (6Mb)
11.2
In addition to the PORT, LAT and TRIS registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This
is controlled by the Open-Drain Control register,
ODCx, associated with each port. Setting any of the
bits configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs higher than V
tolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
See “Pin Diagrams” for the available pins and their
functionality.
11.3
The AD1PCFGL and TRIS registers control the opera-
tion of the analog-to-digital (A/D) port pins. The port
pins that are to function as analog inputs must have
their corresponding TRIS bit set (input). If the TRIS bit
is cleared (output), the digital output level (V
is converted.
The AD1PCFGL register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
EXAMPLE 11-1:
DS70291D-page 164
MOV
MOV
NOP
btss
0xFF00, W0
W0, TRISBB
PORTB, #13
Open-Drain Configuration
Configuring Analog Port Pins
IH
specification.
DD
PORT WRITE/READ EXAMPLE
(e.g., 5V) on any desired 5V
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
; Next Instruction
OH
or V
Preliminary
OL
)
11.4
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be an NOP, as shown in Example 11-1.
11.5
The input change notification function of the I/O ports
allows
dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/
X04 devices to generate interrupt requests to the
processor in response to a change-of-state on selected
input pins. This feature can detect input change-of-
states even in Sleep mode, when the clocks are
disabled. Depending on the device pin count, up to 21
external signals (CNx pin) can be selected (enabled) for
generating an interrupt request on a change-of-state.
Four control registers are associated with the CN mod-
ule. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
push-button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
Note:
I/O Port Write/Read Timing
Input Change Notification
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
the
© 2009 Microchip Technology Inc.
dsPIC33FJ32MC302/304,
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