5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 90

• Manufacturer Part Number: 5M240ZT100C5N
• Description: IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M240ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 192
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5–4
MAX V Device Handbook
1
Figure 5–3
Figure 5–3. MAX V Device Compatibility with 5.0-V CMOS Devices
The open-drain pin never drives high, only low or tri-state. When the open-drain pin
is active, it drives low. When the open-drain pin is inactive, the pin is tri-stated and
the trace pulls up to 5.0 V by the external resistor. The purpose of enabling the I/O
clamp diode is to protect the MAX V device’s I/O pins. The 3.3-V V
the I/O clamp diodes causes the voltage at point A to clamp at 4.0 V, which meets the
MAX V device’s reliability limits when the trace voltage exceeds 4.0 V. The device
operates successfully because a 5.0-V input is within its input specification.
The I/O clamp diode is only supported in the 5M1270Z and 5M2210Z devices’ I/O
Bank 3. You must have an external protection diode for the other I/O banks in the
5M1270Z and 5M2210Z devices and all the I/O pins in the 5M40Z, 5M80Z, 5M160Z,
5M240Z, and 5M570Z devices.
The pull-up resistor value must be small enough for a sufficient signal rise time, but
large enough so that it does not violate the I
MAX V devices.
The maximum MAX V device I
I/O output.
for the 3.3-V LVTTL/LVCMOS I/O standard for MAX V devices. The Quartus II
software uses the maximum current strength as the default setting. The PCI I/O
standard is always set to 20 mA with no alternate setting.
Table 5–1. 3.3-V LVTTL/LVCMOS Programmable Drive Strength (Part 1 of 2)
Note to
(1) This diode is only active after power-up. MAX V devices require an external diode if driven by 5.0 V before
3.3-V LVTTL
power-up.
Figure
shows MAX V device compatibility with 5.0-V CMOS devices.
Table 5–1
5–3:
I/O Standard
Model as R
lists the programmable drive strength settings that are available
V
INT
IN
OL
Open Drain
3.3 V
V
depends on the programmable drive strength of the
CCIO
VSS
V
OUT
(1)
V
Chapter 5: Using MAX V Devices in Multi-Voltage Systems
CCIO
A
OL
(output low) specification of the
I
V
OH
CCIO
/I
OL
R
EXT
Current Strength Setting (mA)
5.0 V ± 0.5 V
December 2010 Altera Corporation
5.0-V CMOS
Device
16
8
5.0-V Device Compatibility
CCIO
supplied to