5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 94

• Manufacturer Part Number: 5M240ZT100C5N
• Description: IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M240ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 192
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5–8
Power-Up Sequencing
Document Revision History
Table 5–4. Document Revision History
MAX V Device Handbook
December 2010
Date
1
Version
For signals with a duty cycle greater than 30% on MAX V input pins, Altera
recommends using a V
signals with a duty cycle less than 30%, the V
MAX V devices are designed to operate in multi-voltage environments where it may
be difficult to control power sequencing. Therefore, MAX V devices are designed to
tolerate any possible power-up sequence. Either V
power to the device and 3.3-, 2.5-, 1.8-, 1.5-, or 1.2-V input signals can drive the
devices without special precautions before V
can operate with a V
When V
device, a delay between V
occur until both power supplies are in their recommended operating range. When
V
connected to V
Thus, any transition on TCK can cause the state machine to transition to an unknown
JTAG state, leading to incorrect operation when V
disable the JTAG state during the power-up sequence, pull TCK low to ensure that an
inadvertent rising edge does not occur on TCK.
Table 5–4
1.0
CCINT
Initial release.
is powered-up, the IEEE Std. 1149.1 JTAG circuitry is active. If TMS and TCK are
CCIO
lists the revision history for this chapter.
and V
CCIO
CCINT
and V
CCIO
CCIO
are supplied from different power sources to a MAX V
voltage level that is higher than the V
CCIO
CCIO
voltage of 3.0 V to guarantee long-term I/O reliability. For
is not powered-up, the JTAG signals are left floating.
and V
CCINT
Chapter 5: Using MAX V Devices in Multi-Voltage Systems
Changes
may occur. Normal operation does not
CCINT
CCIO
voltage can be 3.3 V.
CCIO
or V
CCINT
CCIO
is finally powered-up. To
or V
is applied. MAX V devices
December 2010 Altera Corporation
CCIO
CCINT
can initially supply
level.
Power-Up Sequencing