5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 52

• Manufacturer Part Number: 5M240ZT100C5N
• Description: IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M240ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 192
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3–10
Power Consumption
Timing Model and Specifications
Figure 3–2. Timing Model for MAX V Devices
MAX V Device Handbook
I/O Pin
INPUT
I/O Input Delay
f
f
t
IN
You can use the Altera
Analyzer to estimate the device power.
For more information about these power analysis tools, refer to the
Power Estimator for Altera CPLDs User Guide
in volume 3 of the Quartus II Handbook.
MAX V devices timing can be analyzed with the Altera Quartus
of industry-standard EDA simulators and timing analyzers, or with the timing model
shown in
MAX V devices have predictable internal delays that allow you to determine the
worst-case timing of any design. The software provides timing simulation,
point-to-point delay prediction, and detailed timing analysis for device-wide
performance evaluation.
You can derive the timing characteristics of any signal path from the timing model
and parameters of a particular device. You can calculate external timing parameters,
which represent pin-to-pin timing delays, as the sum of the internal parameters.
For more information, refer to
Input Routing
Global Input Delay
Memory
Delay
Flash
User
t
DL
t
GLOB
Figure
Data-In/LUT Chain
3–2.
To Adjacent LE
Register Control
®
LUT Delay
t
Logic Element
Delay
PowerPlay Early Power Estimator and PowerPlay Power
LUT
t
C
t
R4
AN629: Understanding Timing in Altera
t
COMB
t
t
t
t
PRE
CLR
CO
SU
t
H
Register Delays
Chapter 3: DC and Switching Characteristics for MAX V Devices
t
C4
and the
Data-Out
Combinational Path Delay
From Adjacent LE
PowerPlay Power Analysis
Output Routing
t
Delay
FASTIO
t
IODR
t
IOE
Output and Output Enable
®
May 2011 Altera Corporation
II software, a variety
Data Delay
Output
Delay
t
PowerPlay Early
t
t
OD
XZ
ZX
CPLDs.
Power Consumption
chapter
I/O Pin