EPM7160SQC160-10N Altera, EPM7160SQC160-10N Datasheet - Page 9

• Manufacturer Part Number: EPM7160SQC160-10N
• Description: IC PLD EEPROM 160 MACROCELL 10NS QFP-160
• Manufacturer: Altera
• Series: MAX 7000Sr

Specifications of EPM7160SQC160-10N

• Cpld Type: EEPROM
• No. Of Macrocells: 160
• No. Of I/o's: 104
• Propagation Delay: 10ns
• Global Clock Setup Time: 3.4ns
• Frequency: 149.3MHz
• Supply Voltage Range: 4.75V To 5.25V
• Family Name: MAX 7000S
• Memory Type: EEPROM
• # Macrocells: 160
• Number Of Usable Gates: 3200
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 10
• # I/os (max): 104
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell
Altera Corporation
36 Signals
from PIA
Logic Array
Product Ter
16 Expander
T T ms
Each LAB is fed by the following signals:
■
■
■
Macrocells
The MAX 7000 macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists
of three functional blocks: the logic array, the product-term select
matrix, and the programmable register. The macrocell of EPM7032,
EPM7064, and EPM7096 devices is shown in
Product-
Select
Matrix
Ter
T T m
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used
for fast setup times for MAX 7000E and MAX 7000S devices
Shared Logic
Expanders
Parallel Logic
Expanders
(from other
macrocells)
MAX 7000 Programmable Logic Device Family Data Sheet
Global
Clear
Select
Clear
Global
Clocks
2
VCC
Enable
Clock/
Select
Fast Input
Select
D/T
ENA
Figure
CLRN
PRN
to PIA
Q
Programmable
Register
Register
3.
Bypass
From
I/O pin
To I/O
Control
Block
9