EPM7256AEQC208-7N Altera, EPM7256AEQC208-7N Datasheet - Page 35

• Manufacturer Part Number: EPM7256AEQC208-7N
• Description: IC PLD EEPROM 256 MACROCELL 7.5NS QFP208
• Manufacturer: Altera
• Series: MAX 7000AEr

Specifications of EPM7256AEQC208-7N

• Cpld Type: EEPROM
• No. Of Macrocells: 256
• No. Of I/o's: 164
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 3.9ns
• Frequency: 172.4MHz
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Altera Corporation
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Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
Table 18. EPM7032AE Internal Timing Parameters (Part 1 of 2)
Input pad and buffer delay
I/O input pad and buffer
delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = on
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = on
V
Output buffer disable delay C1 = 5 pF
Register setup time
Register hold time
Register setup time of fast
input
Register hold time of fast
input
Register delay
Combinatorial delay
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
Conditions
MAX 7000A Programmable Logic Device Data Sheet
Min
1.3
0.6
1.0
1.5
-4
Max
0.7
0.7
2.3
1.9
0.5
1.5
0.6
0.0
0.8
1.3
5.8
4.0
4.5
9.0
4.0
0.7
0.6
Note (1)
Speed Grade
Min
2.0
1.0
1.5
1.5
-7
Max
1.2
1.2
2.8
3.1
0.8
2.5
1.0
0.0
1.3
1.8
6.3
4.0
4.5
9.0
4.0
1.2
1.0
Min
2.8
1.3
1.5
1.5
-10
Max
10.0
1.2
1.5
1.5
3.4
4.0
1.0
3.3
0.0
1.8
2.3
6.8
5.0
5.5
5.0
1.5
1.3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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