EPF8282ALC84-4N Altera, EPF8282ALC84-4N Datasheet - Page 25

• Manufacturer Part Number: EPF8282ALC84-4N
• Description: IC, PLD, 208 MACROCELL, 60MHZ, PLCC-84
• Manufacturer: Altera
• Series: FLEX 8Kr

Specifications of EPF8282ALC84-4N

• No. Of Macrocells: 208
• No. Of I/o's: 64
• Global Clock Setup Time: 1.2ns
• Frequency: 60MHz
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Family Name: FLEX 8000
• Number Of Usable Gates: 2500
• Number Of Logic Blocks/elements: 208
• # Registers: 282
• # I/os (max): 78
• Frequency (max): 125MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 5V
• Logic Cells: 208
• Device System Gates: 2500
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Altera Corporation
The instruction register length for FLEX 8000 devices is three bits.
shows the boundary-scan register length for FLEX 8000 devices.
FLEX 8000 devices that support JTAG include weak pull-ups on the JTAG
pins.
Figure 14. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A
JTAG Waveforms
Table 8
EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices.
Captured
Table 7. FLEX 8000 Boundary-Scan Register Length
Driven
Signal
Signal
to Be
to Be
TMS
TDO
TCK
TDI
Figure 14
EPF8282A, EPF8282AV
EPF8636A
EPF8820A
EPF81500A
shows the timing parameters and values for EPF8282A,
Device
shows the timing requirements for the JTAG signals.
t
JCH
FLEX 8000 Programmable Logic Device Family Data Sheet
t
JSZX
t
JPZX
t
JCP
t
JSSU
t
JCL
t
JSH
t
t
JPCO
JSCO
t
JPSU
Boundary-Scan Register Length
t
t
273
417
465
645
JPH
JSXZ
t
JPXZ
Table 7
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