EPM7256AEQC208-10N Altera, EPM7256AEQC208-10N Datasheet - Page 13

• Manufacturer Part Number: EPM7256AEQC208-10N
• Description: IC PLD EEPROM 256 MACROCELL 10NS QFP-208
• Manufacturer: Altera
• Series: MAX 7000AEr

Specifications of EPM7256AEQC208-10N

• Cpld Type: EEPROM
• No. Of Macrocells: 256
• No. Of I/o's: 164
• Propagation Delay: 10ns
• Global Clock Setup Time: 3.9ns
• Frequency: 90.9MHz
• Supply Voltage Range: 3V To 3.6V
• Family Name: MAX 7000A
• Memory Type: EEPROM
• # Macrocells: 256
• Number Of Usable Gates: 5000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 16
• # I/os (max): 164
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MAX 7000A Programmable Logic Device Data Sheet
Figure 5. MAX 7000A PIA Routing
To LAB
PIA Signals
While the routing delays of channel-based routing schemes in masked or
FPGAs are cumulative, variable, and path-dependent, the MAX 7000A
PIA has a predictable delay. The PIA makes a design’s timing
performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V
.
Figure 6
shows the I/O
CC
control block for MAX 7000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
Altera Corporation
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