CAT24C05WI-GT3 CATALYST SEMICONDUCTOR, CAT24C05WI-GT3 Datasheet

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CAT24C05WI-GT3

Manufacturer Part Number
CAT24C05WI-GT3
Description
IC, EEPROM, 4KBIT, SERIAL, 400KHZ SOIC-8
Manufacturer
CATALYST SEMICONDUCTOR
Datasheet
1.CAT24C03YI-GT3.pdf (14 pages)

Specifications of CAT24C05WI-GT3

Memory Size
4Kbit
Memory Configuration
512 X 8 / 256 X 16
Ic Interface Type
I2C
Clock Frequency
400kHz
Supply Voltage Range
1.8V To 5.5V
Memory Case Style
SOIC
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
CAT24C05WI-GT3
Manufacturer:
ON Semiconductor
Quantity:
2 350
CAT24C03, CAT24C05
2-Kb and 4-Kb I
EEPROM with Partial Array
Write Protection
Description
organized internally as 16/32 pages of 16 bytes each, for a total of
256x8/512x8 bits. These devices support both Standard (100 kHz) as
well as Fast (400 kHz) I
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
taking the WP pin High.
CAT24C03 or four CAT24C05 devices on the same bus.
Features
•
•
•
•
•
•
•
•
•
•
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 3
The CAT24C03/05 is a 2−Kb/4−Kb CMOS Serial EEPROM device
Data is written by providing a starting address, then loading 1 to 16
Write operations can be inhibited for upper half of memory by
External address pins make it possible to address up to eight
(SCL and SDA)
Compliant
Supports Standard and Fast I
1.8 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Upper Half of Memory
Schmitt Triggers and Noise Suppression Filters on I
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
A
2
, A
1
SCL
, A
WP
0
Figure 1. Functional Symbol
2
CAT24C03
CAT24C05
C protocol.
V
V
CC
SS
2
C Protocol
2
C Serial
SDA
2
C Bus Inputs
1
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
CASE 646AA
L SUFFIX
A0, A1, A2
Pin Name
PDIP−8
CAT24C05/03
SDA
SCL
V
V
WP
NC
NC/A
CC
A
A
SS
SDA
SCL
V
1
2
ORDERING INFORMATION
V
CASE 948AL
/A
/A
SS
SS
PIN CONFIGURATIONS
Y SUFFIX
TSSOP8
0
1
2
TSSOP (Y), TDFN (VP2)
http://onsemi.com
PDIP (L), SOIC (W),
PIN FUNCTION
TSOT−23 (TD)
CASE 419AE
TD SUFFIX
(Top Views)
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
No Connect
TSOT−23
1
2
3
1
2
3
4
Publication Order Number:
CASE 511AK
5
4
VP2 SUFFIX
8
7
6
5
Function
TDFN8
CASE 751BD
WP
V
V
WP
SCL
SDA
CC
CAT24C03/D
W SUFFIX
CC
SOIC−8

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CAT24C05WI-GT3 Summary of contents

Page 1

CAT24C03, CAT24C05 2-Kb and 4-Kb I EEPROM with Partial Array Write Protection Description The CAT24C03/ 2−Kb/4−Kb CMOS Serial EEPROM device organized internally as 16/32 pages of 16 bytes each, for a total of 256x8/512x8 bits. These devices support ...

Page 2

Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Storage Temperature Voltage on any pin with respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is ...

Page 3

Table 4. PIN IMPEDANCE CHARACTERISTICS ( −40°C to +85°C, unless otherwise specified Symbol Parameter C (Note 4) SDA I/O Pin Capacitance IN Input Capacitance (Other Pins) I (Note 5) WP ...

Page 4

Power−On Reset (POR) The CAT24C03/05 incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The CAT24C03/05 device will power up into Standby mode after V exceeds the POR trigger level and will ...

Page 5

SCL SDA START CONDITION BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START SCL t SU:STA t HD:STA SDA IN SDA OUT Figure 2. START/STOP Conditions ...

Page 6

Byte Write In Byte Write mode, the Master sends the START condition and the Slave address with the R/W bit set to zero to the Slave. After the Slave generates an acknowledge, the Master sends the byte address that is ...

Page 7

SCL th SDA 8 Bit Byte n S BUS ACTIVITY SLAVE R MASTER ADDRESS SLAVE ADDRESS BYTE 1 SCL a 7 SDA WP ACK t WR STOP ...

Page 8

Immediate Read Upon receiving a Slave address with the R/W bit set to ‘1’, the CAT24C03/05 will interpret this as a request for data residing at the current byte address in memory. The CAT24C03/05 will acknowledge the Slave address, will ...

Page 9

PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...

Page 10

PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...

Page 11

E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...

Page 12

D E PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.20 0.25 D 1.90 2.00 D2 1.30 1.40 E 2.90 3.00 E2 1.20 1.30 e 0.50 TYP ...

Page 13

TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-193. PACKAGE DIMENSIONS TSOT−23, 5 LEAD CASE 419AE−01 ISSUE O SYMBOL MIN A A1 0.01 A2 ...

Page 14

Example of Ordering Information Prefix Device # Suffix CAT 24C03 Y Company ID Product Number 24C03 24C05 Package L: PDIP W: SOIC, JEDEC Y: TSSOP VP2: TDFN TD: TSOT 9. All packages are RoHS−compliant (Lead−free, Halogen−free). 10. The standard lead ...

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