CAT93C56LI-G CATALYST SEMICONDUCTOR, CAT93C56LI-G Datasheet - Page 9

• Manufacturer Part Number: CAT93C56LI-G
• Description: IC, EEPROM, 2KBIT, SERIAL, 2MHZ, DIP-8
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT93C56LI-G

• Memory Size: 2Kbit
• Memory Configuration: 256 X 8 / 128 X 16
• Ic Interface Type: Microwire
• Clock Frequency: 2MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Erase All
(Chip Select) pin must be deselected for a minimum of
t
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
CSMIN
Upon receiving an ERAL command (Figure 7), the CS
DO
CS
SK
DO
CS
SK
DI
DI
. The falling edge of CS will start the self clocking
1
1
0
0
HIGH−Z
0
0
0
1
1
0
Figure 8. WRAL Instruction Timing
Figure 7. ERAL Instruction Timing
http://onsemi.com
9
Write All
(Chip Select) pin must be deselected for a minimum of
t
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the CAT93C56/57 can be determined by selecting the device
and polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
CSMIN
D
Upon receiving a WRAL command and data, the CS
N
t
SV
(Figure 8). The falling edge of CS will start the self
D
t
EW
0
STATUS VERIFY
t
BUSY
CS
t
SV
t
READY
EW
STATUS VERIFY
BUSY
t
CSMIN
t
READY
STANDBY
HZ
HIGH−Z
STANDBY
HIGH−Z
t
HZ