CAT28F010G-12T CATALYST SEMICONDUCTOR, CAT28F010G-12T Datasheet - Page 11

• Manufacturer Part Number: CAT28F010G-12T
• Description: IC, FLASH, 1MBIT, 120NS, LCC-32
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT28F010G-12T

• Memory Type: Flash
• Memory Size: 1Mbit
• Memory Configuration: 128K X 8
• Access Time: 120ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: PLCC
• No. Of Pins: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Erase Mode
During the first Write cycle, the command 20H is written
into the command register. In order to commence the
erase operation, the identical command of 20H has to be
written again into the register. This two-step process
ensures against accidental erasure of the memory con-
tents. The final erase cycle will be stopped at the rising
edge of WE, at which time the Erase Verify command
(A0H) is sent to the command register. During this cycle,
the address to be verified is sent to the address bus and
latched when WE goes low. An integrated stop timer
allows for automatic timing control over this operation,
eliminating the need for a maximum erase timing speci-
fication. Refer to AC Characteristics (Program/Erase)
for specific timing parameters.
Figure 6. A.C. Timing for Programming Operation
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
ADDRESSES
DATA (I/O)
WE (W)
OE (G)
CE (E)
V CC POWER-UP
V CC
V PP
& STANDBY
5.0V
0V
V PPH
V PPL
t GHWL
HIGH-Z
SETUP PROGRAM
COMMAND
t VPEL
t DS
t WC
t CH
t WP
t CS
t WPH
DATA IN
= 40H
t AS
LATCH ADDRESS
& DATA
t DH
t DS
t AH
DATA IN
PROGRAMMING
t WP
t CH
t DH
11
t CS
t WHWH1
Erase-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
Programming Mode
The programming operation is initiated using the pro-
gramming algorithm of Figure 7. During the first write
cycle, the command 40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
COMMAND
PROGRAM
t WP
VERIFY
t DS
t WC
DATA IN
= C0H
t DH
t CH
t WHGL
t OLZ
t OE
t LZ
t CE
VERIFICATION
PROGRAM
t RC
DATA OUT
VALID
V CC POWER-DOWN/
Doc. No. MD-1019, Rev. G
CAT28F010
STANDBY
t EHQZ
t DF
t OH
28F010 F08