M25P80-VMN6P NUMONYX, M25P80-VMN6P Datasheet - Page 29
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M25P80-VMN6P
Manufacturer Part Number
M25P80-VMN6P
Description
MEMORY, FLASH, SERIAL, 8MB, 8NSOIC
Manufacturer
NUMONYX
Datasheet
1.M25P80-VMP6G.pdf
(57 pages)
Specifications of M25P80-VMN6P
Memory Size
8Mbit
Clock Frequency
75MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
NSOIC
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Package / Case
NSOIC
Memory Type
Flash
Memory Configuration
1M X 8
Interface Type
Serial, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M25P80-VMN6P
Manufacturer:
MICRON
Quantity:
20 000
Part Number:
M25P80-VMN6PBA
Manufacturer:
ST
Quantity:
20 000
M25P80
Instructions
6.8
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Figure
14.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see
Table 15: AC
characteristics (75 MHz
operation)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is t
) is initiated. While the Page Program cycle is in progress, the Status Register
PP
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see
Table 3
and
Table
2) is not executed.
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