SST25VF040B-50-4I-QAF SILICON STORAGE TECHNOLOGY, SST25VF040B-50-4I-QAF Datasheet - Page 15

• Manufacturer Part Number: SST25VF040B-50-4I-QAF
• Description: 4M FLASH MEMORY, SPI EEPROM, WSON-8
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25VF040B-50-4I-QAF

• Memory Size: 4Mbit
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: WSON
• No. Of Pins: 8
• Svhc: No SVHC (18-Jun-2010)
• Device: RoHS Compliant
• Package / Case: WSON
• Memory Type: Flash
• Memory Configuration: 512K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes

4 Mbit SPI Serial Flash
SST25VF040B
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the
selected 32 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. The
64-KByte Block-Erase instruction clears all bits in the
selected 64 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. Prior to
any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the
duration of any command sequence. The 32-Kbyte Block-
Erase instruction is initiated by executing an 8-bit com-
mand, 52H, followed by address bits [A
[A
©2006 Silicon Storage Technology, Inc.
MS
FIGURE 12: 32-KB
FIGURE 13: 64-KB
-A
15
] (A
MS
= Most Significant Address) are used to
YTE
YTE
B
B
SCK
SCK
CE#
LOCK
CE#
LOCK
SO
SO
SI
SI
-E
-E
MODE 3
MODE 0
MODE 3
MODE 0
RASE
RASE
23
-A
0
]. Address bits
MSB
MSB
S
S
0 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 7 8
EQUENCE
EQUENCE
D8
52
HIGH IMPEDANCE
HIGH IMPEDANCE
15
MSB
MSB
determine block address (BA
be V
is executed. The 64-Kbyte Block-Erase instruction is initi-
ated by executing an 8-bit command D8H, followed by
address bits [A
determine block address (BA
be V
is executed. The user may poll the Busy bit in the software
status register or wait T
self-timed 32-KByte Block-Erase or 64-KByte Block-Erase
cycles. See Figures 12 and 13 for the 32-KByte Block-
Erase and 64-KByte Block-Erase sequences.
ADDR
ADDR
IL
IL
15 16
15 16
or V
or V
ADDR
ADDR
IH.
IH.
CE# must be driven high before the instruction
CE# must be driven high before the instruction
23 24
23 24
23
1295 63KBlkEr.0
-A
1295 32KBklEr.0
ADDR
ADDR
0
]. Address bits [A
BE
31
31
for the completion of the internal
X
X
), remaining address bits can
), remaining address bits can
MS
S71295-01-000
-A
15
] are used to
Data Sheet
1/06