SST39SF040-70-4I-NHE SILICON STORAGE TECHNOLOGY, SST39SF040-70-4I-NHE Datasheet
SST39SF040-70-4I-NHE
Specifications of SST39SF040-70-4I-NHE
Available stocks
Related parts for SST39SF040-70-4I-NHE
SST39SF040-70-4I-NHE Summary of contents
Page 1
... Chip-Erase Time (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 2 seconds (typical) for SST39SF010A 4 seconds (typical) for SST39SF020A 8 seconds (typical) for SST39SF040 • End-of-Write Detection – Toggle Bit – Data# Polling • TTL I/O Compatibility • JEDEC Standard – ...
Page 2
... WE# pulse, while the command (30H) ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods ...
Page 3
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data# Polling ( When the SST39SF010A/020A/040 are in the internal Pro- gram operation, any attempt to read DQ complement of the true data. Once the Program operation is completed, DQ will produce true data. Note that even 7 though DQ may have valid data immediately following the ...
Page 4
... Address Buffers & Latches CE# OE# WE# FIGURE 1: Functional Block Diagram SST39SF040 SST39SF020A DQ0 DQ0 FIGURE 2: Pin Assignments for 32-lead PLCC ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 X-Decoder Control Logic SST39SF010A 32-lead PLCC Top View 10 24 ...
Page 5
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 SST39SF040 SST39SF020A SST39SF010A A11 A11 A11 A13 A13 A13 A14 A14 A14 A17 A17 NC WE# WE# WE A18 NC NC A16 A16 A16 A15 A15 A15 A12 A12 A12 FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 14mm) ...
Page 6
... TABLE 3: Operation Modes Selection Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode 1. X can but no other value ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 -A address lines will select the sector for SST39SF040 18 CE# OE# WE ...
Page 7
... SST39SF010A Device ID = B5H, is read with A SST39SF020A Device ID = B6H, is read with A SST39SF040 Device ID = B7H, is read with A 6. Both Software ID Exit operations are equivalent Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied ...
Page 8
... This parameter is measured only for initial qualification and after a design or process change that could affect this parameter endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a END higher minimum specification. ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 1 = 4.5-5.5V DD Limits Min Max ...
Page 9
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 AC CHARACTERISTICS TABLE 9: Read Cycle Timing Parameters V Symbol Parameter T Read Cycle Time RC T Chip Enable Access Time CE T Address Access Time AA T Output Enable Access Time CE# Low to Active Output CLZ 1 T OE# Low to Active Output ...
Page 10
... OE# CE 7-0 SW0 Note Most significant address for SST39SF010A FIGURE 6: WE# Controlled Program Cycle Timing Diagram ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 OLZ T T CLZ DATA VALID for SST39SF020A, and A for SST39SF040 17 18 INTERNAL PROGRAM OPERATION STARTS ...
Page 11
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 5555 ADDRESS CPH AS OE# WE 7-0 SW0 Note Most significant address for SST39SF010A FIGURE 7: CE# Controlled Program Cycle Timing Diagram ADDRESS A MS-0 CE# OE# WE Note Most significant address for SST39SF010A FIGURE 8: Data# Polling Timing Diagram © ...
Page 12
... Table 10 Sector Address Most significant address for SST39SF010A FIGURE 10: WE# Controlled Sector-Erase Timing Diagram ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 OEH T OE Note for SST39SF020A, and SIX-BYTE CODE FOR SECTOR-ERASE 5555 5555 2AAA ...
Page 13
... Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10 Sector Address Most significant address for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE 11: WE# Controlled Chip-Erase Timing Diagram Three-byte Sequence for Software ID Entry ...
Page 14
... THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 2AAA ADDRESS A 14 7-0 CE# OE WE# SW0 FIGURE 13: Software ID Exit and Reset ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 5555 IDA T WHP SW1 SW2 14 1147 F10.0 S71147-09-000 01/10 ...
Page 15
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 V IHT INPUT V ILT AC test inputs are driven at V (3.0V) for a logic “1” and V IHT and outputs are V (1.5V) and FIGURE 14: AC Input/Output Reference Waveforms TO DUT FIGURE 15: A Test Load Example ©2010 Silicon Storage Technology, Inc. ...
Page 16
... Data Sheet FIGURE 16: Byte-Program Algorithm ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of ...
Page 17
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Internal Timer Byte Program/Erase Initiated Wait SCE Program/Erase Completed FIGURE 17: Wait Options ©2010 Silicon Storage Technology, Inc. Toggle Bit Byte Program/Erase Initiated Read byte Read same No byte No Does DQ 6 match? Yes Program/Erase Completed ...
Page 18
... Address: 5555H Wait T IDA Read Software ID FIGURE 18: Software Product Command Flowcharts ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Software Product ID Exit & Reset Command Sequence Load data: AAH Load data: F0H Address: 5555H Address: XXH ...
Page 19
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Chip-Erase Command Sequence Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H ...
Page 20
... Data Sheet PRODUCT ORDERING INFORMATION SST 39 SF 010A - XXXX - XX ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 - XXX X Environmental Attribute Package Modifier Package Type Temperature Range Minimum Endurance Read Access Speed Version Device Density Voltage Product Series ...
Page 21
... SST39SF040-55-4C-NHE SST39SF040-55-4C-WHE SST39SF040-70-4C-NHE SST39SF040-70-4C-WHE SST39SF040-55-4I-NHE SST39SF040-55-4I-WHE SST39SF040-70-4I-NHE SST39SF040-70-4I-WHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2010 Silicon Storage Technology, Inc. SST39SF010A-70-4C-PHE SST39SF020A-70-4C-PHE ...
Page 22
... Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. FIGURE 20: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 SIDE VIEW .112 .106 .029 .040 .020 R. x 30˚ ...
Page 23
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Pin # 1 Identifier 12.50 12.30 0.70 0.50 14.20 13.80 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. ...
Page 24
... All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. FIGURE 22: 32-pin Plastic Dual In-line Pins (PDIP) SST Package Code: PH ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 1.655 1.645 .200 .170 .150 ...
Page 25
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 TABLE 11: Revision History Number 02 • 2002 Data Book 03 • Changes to Table 5 on page 8 – Added footnote for MPF power usage and Typical conditions – Clarified the Test Conditions for Power Supply Current and Read parameters – ...