M25P16-VMF6P FARNELL, M25P16-VMF6P Datasheet - Page 22

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M25P16-VMF6P

Manufacturer Part Number
M25P16-VMF6P
Description
IC, FLASH, 16MBIT, 75MHZ, SOIC-16
Manufacturer
FARNELL
Datasheet

Specifications of M25P16-VMF6P

Memory Type
Flash
Memory Size
16Mbit
Memory Configuration
2M X 8
Ic Interface Type
Serial, SPI
Clock Frequency
75MHz
Access Time
1.4ms
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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6.4.4
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SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and
the Write Status Register (WRSR) instruction is no longer accepted for execution.
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
S
C
D
Q
sequence
0
High Impedance
1
2
Instruction
3
4
5
6
7
MSB
7
8
6
Status Register Out
9 10 11 12 13 14 15
5
4
3
2
1
0
MSB
7
6
Status Register Out
5
4
3
2
1
0
7
AI02031E

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