CAT24C44VI-T3 CATALYST SEMICONDUCTOR, CAT24C44VI-T3 Datasheet - Page 6

IC, NVSRAM, 256BIT, SOIC-8

CAT24C44VI-T3

Manufacturer Part Number
CAT24C44VI-T3
Description
IC, NVSRAM, 256BIT, SOIC-8
Manufacturer
CATALYST SEMICONDUCTOR
Datasheet

Specifications of CAT24C44VI-T3

Memory Size
256bit
Memory Configuration
16 X 16
Ic Interface Type
Serial
Supply Voltage Range
4.5V To 5.5V
Memory Case Style
SOIC
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
WREN/WRDS
The CAT24C44 powers up in the program disable state
(the “write enable latch” is reset). Any programming after
power-up or after a WRDS (RAM write/EEPROM store
disable) instruction must first be preceded by the WREN
(RAM write/EEPROM store enable) instruction. Once
writing/storing is enabled, it will remain enabled until
power to the device is removed, the WRDS instruction is
sent, or an EEPROM store has been executed (STO).
Figure 3. Read Cycle Timing
Figure 4. Write Cycle Timing
Doc. No. MD-1083, Rev. T
CAT24C44
DO
CE
SK
CE
SK
DI
DI
SK CYCLE #
V IH
x
6
t DS
t CES
t SKH
HIGH-Z
1
7
1/F SK
t DH
t SKL
t PD
2
8
6
The WRDS (write/store disable) can be used to disable
all CAT24C44 programming functions, and will prevent
any accidental writing to the RAM, or storing to the
EEPROM.
Data can be read normally from the CAT24C44 regard-
less of the “write enable latch” status.
t CEH
D0
n
9
t PD
D1
10
t CDS
Dn
11
Characteristics subject to change without notice
© 2008 SCILLC. All rights reserved.
t Z
HIGH-Z

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