FM24C256-G Ramtron, FM24C256-G Datasheet
FM24C256-G
Specifications of FM24C256-G
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FM24C256-G Summary of contents
Page 1
... EIAJ SOIC Package Pin Configuration caused by VSS Pin Names A0-A2 SDA higher than SCL WP VSS VDD Ordering Information FM24C256-G VDD SCL 3 6 SDA 4 5 Function Device Select Address Serial Data/Address Serial Clock Write Protect Ground Supply Voltage 5V “ ...
Page 2
... SCL falling edge, and clocked in on the SCL rising edge. The SCL input also incorporates a Schmitt trigger input for improved noise immunity. VDD Supply Supply Voltage: 5V VSS Supply Ground Rev. 3.3 Jan. 2011 Address Latch Converter Figure 1. Block Diagram FM24C256 4,096 x 64 FRAM Array 8 Data Latch Page ...
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... This is explained in more detail in the interface section below. Users can expect several obvious system benefits from the FM24C256 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since the write cycle is completed quickly ...
Page 4
... Bits 7-4 define the device type and must be set to 1010b for the FM24C256. These bits allow other types of function types to reside on the 2-wire bus within an identical address range. Bits 3-1 are the device select bits which are equivalent to chip select bits ...
Page 5
... After the address information has been transmitted, data transfer between the bus master and the FM24C256 can begin. For a read operation the FM24C256 will place 8 data bits on the bus then wait for an Acknowledge from the master. If the Acknowledge occurs, the FM24C256 will transfer the next sequential byte ...
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... After each byte, the internal address counter will be incremented. Each time the bus master acknowledges a byte, this indicates that the FM24C256 should read out the next sequential byte. There are four ways to properly terminate a read operation. Failing to properly terminate the read will Rev ...
Page 7
... Therefore, endurance cycles are applied for each read and write access. The FRAM architecture is based on an array of rows and columns. Rows (A14-A6) are subdivided into 8 segments (A5-A3). Each access causes an endurance cycle for a row segment. In the FM24C256, there are Rev. 3.3 Jan. 2011 Address S ...
Page 8
... Std JESD22-A115-A) = 4.5V to 5.5V unless otherwise specified) DD Min Typ 4.5 5 other inputs -0. Stop command issued. DD FM24C256 Ratings -1.0V to +7.0V -1.0V to +7.0V and V < V +1. -55° 125°C 300° C 4kV 400V MSL-1 Max Units Notes 5 200 µA 500 µ ...
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... DD Max Units FM24C256 Max Min Max Units Notes 400 0 1000 kHz 0.6 µs 0.4 µs 0.9 0.55 µs 0.5 µs 0.25 µs 0.25 µ 100 ns 300 300 ns 1 300 ...
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... Write Bus Timing SCL t SU:STO SDA Start Data Retention (V = 4.5V to 5.5V, +85° Parameter Data Retention Rev. 3.3 Jan. 2011 t HIGH 1/fSCL t AA Stop Start t HD:DAT t t SU:DAT HD:STA Stop Start Min Units 45 Years FM24C256 LOW t HD:DAT t SU:DAT t DH Acknowledge t AA Acknowledge Notes Page ...
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... Legend: XXXXXX= part number LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week XXXXXXX-G LLLLLLL FM24C256, “Green” EIAJ SOIC package, Year 2004, Work Week 50 RIC YYWW FM24C256-G A40003S1 RIC 0450 Rev. 3.3 Jan. 2011 Recommended PCB Footprint 5.28 0.10 8 ...
Page 12
... Changed storage temperature. New rev. number and 1 with updated scheme. Changed Data Retention spec. Clarified Package Marking Scheme text and drawings. Removed –SE option from ordering information. Not Recommended for New Designs. No direct replacement alternative, use the FM24W256. FM24C256 st page footer to comply Page ...