FM24C64-G Ramtron, FM24C64-G Datasheet
FM24C64-G
Specifications of FM24C64-G
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FM24C64-G Summary of contents
Page 1
... SOIC (-G) • Grade 3 AEC-Q100 Qualified (-G) Pin Configuration caused by VSS Pin Names A0-A2 SDA SCL WP VSS VDD Ordering Information FM24C64-G FM24C64-GTR FM24C64-S * FM24C64-STR * * End of life. Last time buy June 2009. VDD SCL 3 6 SDA 4 5 Function Device Select Address Serial Data/address ...
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... When WP is low, all addresses may be written. This pin must not be left floating. VDD Supply Supply Voltage: 5V VSS Supply Ground Rev. 3.2 Feb. 2011 Address Latch Converter Figure 1. FM24C64 Block Diagram FM24C64 1,024 x 64 FRAM Array 8 Data Latch ...
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... This is explained in more detail in the interface section below. Users can expect several obvious system benefits from the FM24C64 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly ...
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... If the receiver acknowledges the last byte, this will cause the FM24C64 to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop command. ...
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... After the address information has been transmitted, data transfer between the bus master and the FM24C64 can begin. For a read operation, the FM24C64 will place 8 data bits on the bus then wait for an Acknowledge from the master. If the Acknowledge occurs, the FM24C64 will transfer the next sequential byte ...
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... Current Address & Sequential Read The FM24C64 uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation ...
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... The FRAM architecture is based on an array of rows which are subdivided into segments. Rows (defined by A12-A5) are subdivided into 4 segments (A4-A3). Each access causes an endurance cycle for a row segment. In the FM24C64, there are 8 bytes (defined by A2-A0) per Rev. 3.2 Feb. 2011 Address Start ...
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... DD Min Typ 4.5 5.0 115 400 1 1 -0 other inputs -0. Stop command issued FM24C64 Ratings -1.0V to +7.0V -1.0V to +7.0V and V < V +1. -55° 125°C 300° C 4kV 250V MSL-1 Max Units Notes 5 150 µA 500 µA 1.2 ...
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... DD Max Units FM24C64 Max Min Max Units Notes 400 0 1000 kHz 0.6 µs 0.4 µs 0.9 0.55 µs 0.5 µs 0.25 µs 0.25 µ 100 ns 300 300 ...
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... tHIGH 1/fSCL Valid Valid tAA tDH Data bit 7 Data bit 6 from FM24C64 from FM24C64 5-0 from FM24C64 tHD:STA tHD:DAT tSU:DAT Valid Valid Data/Address bit 7 Data/Address bit 6 Data/Address bit 5-0 to FM24C64 to FM24C64 Min Units 45 Years FM24C64 Equivalent AC Load Circuit 5.5V 1700 Ω ...
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... SOIC Package Marking Scheme Legend: XXXX= part number, P= package type LLLLLLL= lot code XXXXXXX-P RIC=Ramtron Int’l Corp, YY=year, WW=work week LLLLLLL RICYYWW Example: FM24C64, “Green” SOIC package, Year 2004, Work Week 39 FM24C64-G A40003G1 RIC0439 Rev. 3.2 Feb. 2011 FM24C64 ...
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... Changed Data Retention spec. Added ESD and package MSL ratings. New rev. number to comply with new scheme. Added tape and reel ordering information. Added last time buy notice on –S ordering number. Added notation that –G parts are Grade 3. Not Recommended for New Designs. Alternative: FM24C64B. FM24C64 12 cycles. Rewrote Data Retention and ...