AT91SAM7S32B-AU-001 Atmel, AT91SAM7S32B-AU-001 Datasheet - Page 16

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AT91SAM7S32B-AU-001

Manufacturer Part Number
AT91SAM7S32B-AU-001
Description
8-Bit Microcontrollers
Manufacturer
Atmel
Datasheet

Specifications of AT91SAM7S32B-AU-001

Termination Type
SMD
Interface
I2C, SPI, UART
Embedded Interface Type
I2C, SPI, UART
Supply Voltage Max
3.6V
No. Of Adc Inputs
8
Flash Memory Size
32KB
No. Of I/o Pins
21
Core Size
32 Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
7. Processor and Architecture
7.1
7.2
7.3
16
ARM7TDMI Processor
Debug and Test Features
Memory Controller
AT91SAM7S Series Summary
• RISC processor based on ARMv4T Von Neumann architecture
• Two instruction sets
• Three-stage pipeline architecture
• Integrated EmbeddedICE
• Debug Unit
• IEEE1149.1 JTAG Boundary-scan on all digital pins
• Bus Arbiter
• Address decoder provides selection signals for
• Abort Status Registers
• Misalignment Detector
• Remap Command
• Embedded Flash Controller
– Runs at up to 55 MHz, providing 0.9 MIPS/MHz
– ARM
– Thumb
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Two watchpoint units
– Test access port accessible through a JTAG protocol
– Debug communication channel
– Two-pin UART
– Debug communication channel interrupt handling
– Chip ID Register
– Handles requests from the ARM7TDMI and the Peripheral DMA Controller
– Three internal 1 Mbyte memory areas
– One 256 Mbyte embedded peripheral area
– Source, Type and all parameters of the access leading to an abort are saved
– Facilitates debug by detection of bad pointers
– Alignment checking of all data accesses
– Abort generation in case of misalignment
– Remaps the SRAM in place of the embedded non-volatile memory
– Allows handling of dynamic exception vectors
– Embedded Flash interface, up to three programmable wait states
®
high-performance 32-bit instruction set
®
high code density 16-bit instruction set
(embedded in-circuit emulator)
6175IS–ATARM–30-Aug-10

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