PIC16F1826-I/MV Microchip Technology, PIC16F1826-I/MV Datasheet - Page 240
![IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28](/photos/12/13/121305/c04-152_mv_sml.jpg)
PIC16F1826-I/MV
Manufacturer Part Number
PIC16F1826-I/MV
Description
IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(406 pages)
3.PIC16F1826-IP.pdf
(12 pages)
4.PIC16F1826-IP.pdf
(8 pages)
5.PIC16F1826-IP.pdf
(40 pages)
6.PIC16LF1827-ISS.pdf
(400 pages)
Specifications of PIC16F1826-I/MV
Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
3
Interface
EUSART, I2C, SPI
Core Size
8 Bit
Program Memory Size
2kWords
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-UFQFN Exposed Pad
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 KB
Interface Type
MI2C, SPI, EUSART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1826-IP PDF datasheet #3
- PIC16F1826-IP PDF datasheet #4
- PIC16F1826-IP PDF datasheet #5
- PIC16LF1827-ISS PDF datasheet #6
- Current page: 240 of 406
- Download datasheet (4Mb)
PIC16F/LF1826/27
24.2.4
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCKx. When the last
bit is latched, the SSPxIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCKx pin. The Idle state is
determined by the CKP bit of the SSPxCON1 register.
While in Slave mode, the external clock is supplied by
the external clock source on the SCKx pin. This exter-
nal clock must meet the minimum high and low times
as specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. The shift register is clocked from the SCKx pin
input and when a byte is received, the device will gen-
erate an interrupt. If enabled, the device will wake-up
from Sleep.
24.2.4.1
The SPI bus can sometimes be connected in a
daisy-chain configuration. The first slave output is con-
nected to the second slave input, the second slave
output is connected to the third slave input, and so on.
The final slave output is connected to the master input.
Each slave sends out, during a second group of clock
pulses, an exact copy of what was received during the
first group of clock pulses. The whole chain acts as
one
daisy-chain feature only requires a single Slave Select
line from the master device.
Figure 24-7 shows the block diagram of a typical
Daisy-Chain connection when operating in SPI Mode.
In a daisy-chain configuration, only the most recent
byte on the bus is required by the slave. Setting the
BOEN bit of the SSPxCON3 register will enable writes
to the SSPxBUF register, even if the previous byte has
not been read. This allows the software to ignore data
that may not apply to it.
DS41391C-page 240
large
Daisy-Chain Configuration
SPI SLAVE MODE
communication
shift
register.
The
Preliminary
24.2.5
The Slave Select can also be used to synchronize com-
munication. The Slave Select line is held high until the
master device is ready to communicate. When the
Slave Select line is pulled low, the slave knows that a
new transmission is starting.
If the slave fails to receive the communication properly,
it will be reset at the end of the transmission, when the
Slave Select line returns to a high state. The slave is
then ready to receive a new transmission when the
Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will even-
tually become out of sync with the master. If the slave
misses a bit, it will always be one bit off in future trans-
missions. Use of the Slave Select line allows the slave
and master to align themselves at the beginning of
each transmission.
The SSx pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SSx pin control
enabled (SSPxCON1<3:0> = 0100).
When the SSx pin is low, transmission and reception
are enabled and the SDOx pin is driven.
When the SSx pin goes high, the SDOx pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the applica-
tion.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SSx pin to
a high level or clearing the SSPxEN bit.
Note 1: When the SPI is in Slave mode with SSx
2: When the SPI is used in Slave mode with
3: While operated in SPI Slave mode the
SLAVE SELECT
SYNCHRONIZATION
SMP bit of the SSPxSTAT register must
remain clear.
pin control enabled (SSPxCON1<3:0> =
0100), the SPI module will reset if the SSx
pin is set to V
CKE set; the user must enable SSx pin
control.
2010 Microchip Technology Inc.
DD
.
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