PIC16F1827-I/SS Microchip Technology, PIC16F1827-I/SS Datasheet - Page 243
![IC, 8BIT MCU, PIC16F, 32MHZ, SSOP-20](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16F1827-I/SS
Manufacturer Part Number
PIC16F1827-I/SS
Description
IC, 8BIT MCU, PIC16F, 32MHZ, SSOP-20
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(406 pages)
3.PIC16F1826-IP.pdf
(12 pages)
4.PIC16F1826-IP.pdf
(8 pages)
5.PIC16F1826-IP.pdf
(40 pages)
6.PIC16LF1827-ISS.pdf
(400 pages)
Specifications of PIC16F1827-I/SS
Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
384Byte
Cpu Speed
32MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Core Size
8 Bit
Program Memory Size
4kWords
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
15
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1827-I/SS
Manufacturer:
NELL
Quantity:
45
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1826-IP PDF datasheet #3
- PIC16F1826-IP PDF datasheet #4
- PIC16F1826-IP PDF datasheet #5
- PIC16LF1827-ISS PDF datasheet #6
- Current page: 243 of 406
- Download datasheet (4Mb)
24.2.6
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx
interrupts should be disabled.
TABLE 24-1:
2010 Microchip Technology Inc.
APFCON0
ANSELA
ANSELB
INTCON
PIE1
PIR1
SSPxBUF
SSPxCON1
SSPxCON3
SSPxSTAT
TRISA
TRISB
Legend:
Note 1:
Name
*
SPI OPERATION IN SLEEP MODE
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.
Page provides register information.
PIC16F/LF1827 only.
Synchronous Serial Port Receive Buffer/Transmit Register
RXDTSEL
TMR1GIE
TMR1GIF
ACKTIM
TRISA7
TRISB7
ANSB7
WCOL
Bit 7
SMP
GIE
—
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
SDO1SEL
SSPxOV
TRISA6
TRISB6
ANSB6
ADIE
PCIE
Bit 6
PEIE
ADIF
CKE
—
SSPxEN
SS1SEL
TMR0IE
TRISA5
TRISB5
ANSB5
RCIE
RCIF
SCIE
Bit 5
D/A
—
P2BSEL
TRISA4
TRISB4
ANSA4
ANSB4
BOEN
Preliminary
INTE
TXIE
Bit 4
TXIF
CKP
P
(1)
CCP2SEL
SSPxM3
SSP1IE
SSP1IF
TRISA3
TRISB3
ANSA3
ANSB3
SDAHT
IOCIE
Bit 3
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
S
(1)
PIC16F/LF1826/27
SSPxM2
P1DSEL
TMR0IF
CCP1IE
CCP1IF
SBCDE
TRISA2
TRISB2
ANSA2
ANSB2
Bit 2
R/W
P1CSEL
SSPxM1
TMR2IE
TMR2IF
TRISA1
TRISB1
ANSA1
ANSB1
AHEN
Bit 1
INTF
UA
CCP1SEL
SSPxM0
TMR1IE
TMR1IF
TRISA0
TRISB0
ANSA0
DHEN
IOCIF
Bit 0
DS41391C-page 243
BF
—
Register
on Page
237*
122
125
130
283
285
282
124
129
91
92
96
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