PIC16LF1827-I/MV Microchip Technology, PIC16LF1827-I/MV Datasheet - Page 400

• Manufacturer Part Number: PIC16LF1827-I/MV
• Description: IC, 8BIT MCU, PIC16LF, 32MHZ, QFN-28
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1827-I/MV

• Controller Family/series: PIC16LF
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 384Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 4kWords
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-UFQFN Exposed Pad
• Processor Series: PIC16LF
• Core: PIC
• Data Ram Size: 256 B
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 16
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF1826/27
Timer0 ....................................................................... 175, 194
Timer1 ............................................................................... 179
Timer2
Timer2/4/6 ......................................................................... 191
Timers
Timing Diagrams
DS41391C-page 400
Associated Registers ................................................ 177
Operation .................................................................. 175
Specifications ............................................................ 365
Associated registers.................................................. 189
Asynchronous Counter Mode ................................... 181
Clock Source Selection ............................................. 180
Interrupt..................................................................... 183
Operation .................................................................. 180
Operation During Sleep ............................................ 183
Oscillator ................................................................... 181
Prescaler ................................................................... 181
Specifications ............................................................ 365
Timer1 Gate
TMR1H Register ....................................................... 179
TMR1L Register ........................................................ 179
Associated registers.................................................. 194
Associated registers.................................................. 194
Timer1
Timer2/4/6
A/D Conversion ......................................................... 367
A/D Conversion (Sleep Mode) .................................. 367
Acknowledge Sequence ........................................... 272
Asynchronous Reception .......................................... 294
Asynchronous Transmission ..................................... 290
Asynchronous Transmission (Back to Back) ............ 290
Auto Wake-up Bit (WUE) During Normal Operation . 306
Auto Wake-up Bit (WUE) During Sleep .................... 306
Automatic Baud Rate Calibration .............................. 304
Baud Rate Generator with Clock Arbitration ............. 265
BRG Reset Due to SDA Arbitration During Start
Brown-out Reset (BOR) ............................................ 363
Brown-out Reset Situations ........................................ 79
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) ..... 276
Bus Collision During a Stop Condition (Case 1) ....... 278
Bus Collision During a Stop Condition (Case 2) ....... 278
Bus Collision During Start Condition (SDA only) ...... 275
Bus Collision for Transmit and Acknowledge............ 274
CLKOUT and I/O....................................................... 361
Clock Synchronization .............................................. 262
Clock Timing ............................................................. 359
Comparator Output ................................................... 165
Enhanced Capture/Compare/PWM (ECCP) ............. 365
Fail-Safe Clock Monitor (FSCM) ................................. 68
First Start Bit Timing ................................................. 266
Full-Bridge PWM Output ........................................... 219
Half-Bridge PWM Output .................................. 217, 224
I
I
I
2
2
2
C Bus Data ............................................................. 373
C Bus Start/Stop Bits.............................................. 372
C Master Mode (7 or 10-Bit Transmission) ............ 269
Reading and Writing ......................................... 181
Selecting Source............................................... 181
T1CON.............................................................. 187
T1GCON ........................................................... 188
TXCON ............................................................. 193
Condition........................................................... 276
(Case 1) ............................................................ 277
(Case 2) ............................................................ 277
Preliminary
Timing Diagrams and Specifications
Timing Parameter Symbology .......................................... 358
Timing Requirements
TMR0 Register.................................................................... 30
TMR1H Register ................................................................. 30
TMR1L Register.................................................................. 30
TMR2 Register.............................................................. 30, 38
TRIS.................................................................................. 342
TRISA Register........................................................... 31, 124
TRISB ............................................................................... 128
TRISB Register........................................................... 31, 129
Two-Speed Clock Start-up Mode........................................ 65
TXCON (Timer2/4/6) Register .......................................... 193
TxCON Register ............................................................... 213
TXREG ............................................................................. 289
TXREG Register ................................................................. 33
TXSTA Register.......................................................... 33, 296
U
USART
V
V
W
Wake-up on Break ............................................................ 305
Wake-up Using Interrupts ................................................. 102
Watchdog Timer (WDT)...................................................... 80
REF
I
I
INT Pin Interrupt ......................................................... 89
Internal Oscillator Switch Timing ................................ 63
PWM Auto-shutdown ................................................ 223
PWM Direction Change ............................................ 220
PWM Direction Change at Near 100% Duty Cycle... 221
PWM Output (Active-High) ....................................... 215
PWM Output (Active-Low) ........................................ 216
Repeat Start Condition ............................................. 267
Reset Start-up Sequence ........................................... 81
Reset, WDT, OST and Power-up Timer ................... 362
Send Break Character Sequence ............................. 307
SPI Master Mode (CKE = 1, SMP = 1) ..................... 370
SPI Mode (Master Mode).......................................... 239
SPI Slave Mode (CKE = 0) ....................................... 371
SPI Slave Mode (CKE = 1) ....................................... 371
Synchronous Reception (Master Mode, SREN) ....... 312
Synchronous Transmission ...................................... 309
Synchronous Transmission (Through TXEN) ........... 309
Timer0 and Timer1 External Clock ........................... 364
Timer1 Incrementing Edge ....................................... 183
Two Speed Start-up.................................................... 66
USART Synchronous Receive (Master/Slave) ......... 369
USART Synchronous Transmission (Master/Slave). 369
Wake-up from Interrupt............................................. 102
PLL Clock ................................................................. 360
I
SPI Mode .................................................................. 372
BRGH Bit .................................................................. 299
Synchronous Master Mode
Modes ....................................................................... 104
Specifications ........................................................... 364
. S
2
2
2
C Master Mode (7-Bit Reception)........................... 271
C Stop Condition Receive or Transmit Mode......... 273
C Bus Data............................................................. 374
EE
Firmware Restart .............................................. 222
Requirements, Synchronous Receive .............. 369
Requirements, Synchronous Transmission...... 369
Timing Diagram, Synchronous Receive ........... 369
Timing Diagram, Synchronous Transmission... 369
ADC Reference Voltage
 2010 Microchip Technology Inc.