PIC18F46K20-E/P Microchip Technology, PIC18F46K20-E/P Datasheet - Page 39

• Manufacturer Part Number: PIC18F46K20-E/P
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, DIP-40
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K20-E/P

• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3936Byte
• Cpu Speed: 64MHz
• No. Of Timers: 4
• Core Size: 8 Bit
• Program Memory Size: 32768 Words
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP, ECCP, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20
• Lead Free Status / Rohs Status: Details

6.0
© 2009 Microchip Technology Inc.
Standard Operating Conditions
Operating Temperature: 25°C is recommended
Param
P12
P13
P14
P15
P16
P17
P18
P19
P20
Note 1:
No.
T
T
T
T
T
T
T
T
T
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/
VERIFY TEST MODE (CONTINUED)
Sym.
HLD
SET
VALID
SET
DLY
HLD
HLD
HIZ
PPDP
Do not allow excess time when transitioning MCLR between V
executions to occur. The maximum transition time is:
1 T
+ 1.5 μs (for EC mode only) where T
T
sheet for the particular device.
OSC
2
3
8
2
3
4
CY
Input Data Hold Time from MCLR/V
V
Data Out Valid from PGC ↑
PGM ↑ Setup Time to MCLR/V
Delay between Last PGC ↓ and MCLR/V
MCLR/V
MCLR/V
Delay from PGC ↑ to PGD High-Z
Hold time after V
is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data
+ T
DD
PWRT
↑ Setup Time to MCLR/V
PP
PP
(if enabled) + 1024 T
/RE3 ↓ to V
/RE3 ↓ to PGM ↓
PP
Characteristic
changes
DD
↓
Advance Information
PP
OSC
PP
CY
/RE3 ↑
/RE3 ↑
is the instruction cycle time, T
PP
(for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only)
/RE3 ↑
PP
/RE3 ↓
PIC18F2XK20/4XK20
Min.
100
10
—
2
2
0
0
3
5
IL
and V
PWRT
IHH
Max.
100
10
—
—
—
—
—
—
—
; this can cause spurious program
is the Power-up Timer period and
Units
nS
μs
ns
ns
μs
ns
μs
s
s
Conditions
DS41297F-page 39