PIC32MX360F256L-80I/BG Microchip Technology, PIC32MX360F256L-80I/BG Datasheet - Page 39

• Manufacturer Part Number: PIC32MX360F256L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F256L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 256 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: EUSART, I2C, SPI
• Rohs Compliant: Yes
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EUART, I2C, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARD
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 4-5:
TABLE 4-6:
Legend:
Note
Legend:
Note
BF80_3220
BF80_3400
BF80_3410
BF80_3420
BF80_3600
BF80_3610
BF80_3620
BF80_3800
BF80_3810
BF80_3820
BF80_5000
BF80_5010
BF80_5020
BF80_5030
BF80_5040
Virtual
Virtual
Addr
Addr
SFR
SFR
1:
1:
OC3CON
OC4CON
OC5CON
I2C1STAT
I2C1CON
I2C1MSK
I2C1BRG
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-
mation.
I2C1ADD
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Regis-
ters” for more information.
OC2RS
OC3RS
OC4RS
OC5RS
Name
OC3R
OC4R
OC5R
Name
SFR
SFR
OUTPUT COMPARE 1-5 REGISTERS MAP
I2C1-2 REGISTERS MAP
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
ACKSTAT
31/15
31/15
Bits
ON
ON
ON
Bits
—
—
—
ON
—
—
—
—
—
—
—
—
TRSTAT
30/14
Bits
30/14
FRZ
FRZ
FRZ
Bits
FRZ
—
—
—
—
—
—
—
—
—
—
—
29/13
SIDL
SIDL
SIDL
Bits
29/13
SIDL
Bits
—
—
—
—
—
—
—
—
—
—
—
—
(1)
SCLREL
28/12
28/12
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STRICT
27/11
27/11
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
26/10
26/10
A10M
(CONTINUED)
Bits
Bits
BCL
—
—
—
—
—
—
—
—
—
—
—
—
—
GCSTAT
DISSLW
25/9
Bits
Bits
25/9
—
—
—
—
—
—
—
—
—
—
—
ADD10
SMEN
Bits
24/8
24/8
Bits
OC2RS<31:0>
OC3RS<31:0>
OC4RS<31:0>
OC5RS<31:0>
—
—
—
—
—
—
—
—
—
—
—
OC3R<31:0>
OC4R<31:0>
OC5R<31:0>
IWCOL
GCEN
Bits
23/7
23/7
Bits
—
—
—
—
—
—
—
—
—
—
—
STREN
I2COV
Bits
22/6
Bits
22/6
I2C1BRG<11:0>
—
—
—
—
—
—
—
—
—
—
—
ACKDT
OC32
OC32
OC32
Bits
21/5
Bits
21/5
D/A
—
—
—
—
—
—
—
—
ADD<9:0>
MSK<9:0>
OCFLT
OCFLT
OCFLT
ACKEN
20/4
Bits
20/4
Bits
—
—
—
—
—
—
—
—
P
OCTSEL
OCTSEL
OCTSEL
RCEN
19/3
Bits
Bits
19/3
—
—
—
—
—
—
—
—
S
18/2
Bits
Bits
18/2
PEN
R/W
—
—
—
—
—
—
—
—
OCM<2:0>
OCM<2:0>
OCM<2:0>
RSEN
Bits
17/1
17/1
Bits
RBF
—
—
—
—
—
—
—
—
Bits
16/0
Bits
16/0
SEN
TBF
—
—
—
—
—
—
—
—