PIC32MX675F256L-80I/BG Microchip Technology, PIC32MX675F256L-80I/BG Datasheet - Page 86
PIC32MX675F256L-80I/BG
Manufacturer Part Number
PIC32MX675F256L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX675F256L-80I/BG
Controller Family/series
PIC32
Ram Memory Size
64KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
256 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F256L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC32MX320F032H-40IPT PDF datasheet
- PIC32MX575F256H-80IMR PDF datasheet #2
- PIC32MX575F256H-80IMR PDF datasheet #3
- PIC32MX575F256H-80IMR PDF datasheet #4
- PIC32MX575F256H-80IPT PDF datasheet #5
- Current page: 86 of 240
- Download datasheet (3Mb)
TABLE 4-30:
TABLE 4-31:
Legend:
Note
Legend:
Note
6100
6110
6120
6130
6100
6110
6120
6130
PORTE
1:
PORTE
1:
TRISE
ODCE
TRISE
ODCE
LATE
LATE
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PORT E REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F512H, PIC32MX695F512H, AND
PIC32MX795F512H DEVICES
PORT E REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F512L, PIC32MX695F512L, AND
PIC32MX795F512L DEVICES
31/15
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28/12
28/12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(1)
27/11
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE9
ODCE9
LATE9
25/9
25/9
RE9
—
—
—
—
—
—
—
—
—
—
—
—
TRISE8
ODCE8
LATE8
24/8
24/8
RE8
—
—
—
—
—
—
—
—
—
—
—
—
Bits
Bits
TRISE7
ODCE7
TRISE7
ODCE7
LATE7
LATE7
23/7
23/7
RE7
RE7
—
—
—
—
—
—
—
—
TRISE6
TRISE6
0DCE6
0DCE6
LATE6
LATE6
22/6
22/6
RE6
RE6
—
—
—
—
—
—
—
—
TRISE5
ODCE5
TRISE5
ODCE5
LATE5
LATE5
21/5
21/5
RE5
RE5
—
—
—
—
—
—
—
—
TRISE4
TRISE4
ODCE4
ODCE4
LATE4
LATE4
20/4
20/4
RE4
RE4
—
—
—
—
—
—
—
—
TRISE3
ODCE3
TRISE3
ODCE3
LATE3
LATE3
19/3
RE3
19/3
RE3
—
—
—
—
—
—
—
—
TRISE2
ODCE2
TRISE2
ODCE2
LATE2
LATE2
18/2
18/2
RE2
RE2
—
—
—
—
—
—
—
—
TRISE1
ODCE1
TRISE1
ODCE1
LATE1
LATE1
17/1
17/1
RE1
RE1
—
—
—
—
—
—
—
—
TRISE0
ODCE0
TRISE0
ODCE0
LATE0
LATE0
16/0
16/0
RE0
RE0
—
—
—
—
—
—
—
—
0000
03FF
0000
xxxx
0000
xxxx
0000
0000
0000
00FF
0000
xxxx
0000
xxxx
0000
0000
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