PIC32MX675F256L-80I/BG Microchip Technology, PIC32MX675F256L-80I/BG Datasheet - Page 89
![IC, 32BIT MCU, PIC32, 80MHZ, BGA-100](/photos/12/13/121347/121-xbga_sml.jpg)
PIC32MX675F256L-80I/BG
Manufacturer Part Number
PIC32MX675F256L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX675F256L-80I/BG
Controller Family/series
PIC32
Ram Memory Size
64KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
256 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F256L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC32MX320F032H-40IPT PDF datasheet
- PIC32MX575F256H-80IMR PDF datasheet #2
- PIC32MX575F256H-80IMR PDF datasheet #3
- PIC32MX575F256H-80IMR PDF datasheet #4
- PIC32MX575F256H-80IPT PDF datasheet #5
- Current page: 89 of 240
- Download datasheet (3Mb)
TABLE 4-36:
TABLE 4-37:
Legend:
Note
Legend:
Note
61C0 CNCON
61D0
61E0
61C0 CNCON
61D0
61E0
1:
1:
CNPUE
CNPUE
CNEN
CNEN
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F512L,
PIC32MX695F512L, AND PIC32MX795F512L DEVICES
CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F512H,
PIC32MX695F512H, AND PIC32MX795F512H DEVICES
CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
CNEN15
CNEN15
31/15
31/15
ON
ON
—
—
—
—
—
—
CNEN14
CNEN14
30/14
30/14
FRZ
FRZ
—
—
—
—
—
—
CNEN13
CNEN13
29/13
29/13
SIDL
SIDL
—
—
—
—
—
—
CNEN12
CNEN12
28/12
28/12
—
—
—
—
—
—
—
—
CNEN11
CNEN11
27/11
27/11
—
—
—
—
—
—
—
—
CNEN10
CNEN10
26/10
26/10
—
—
—
—
—
—
—
—
CNPUE9
CNPUE9
CNEN9
CNEN9
25/9
25/9
—
—
—
—
—
—
—
—
CNPUE8
CNPUE8
(1)
CNEN8
CNEN8
(1)
24/8
24/8
—
—
—
—
—
—
—
—
Bits
Bits
CNPUE7
CNPUE7
CNEN7
CNEN7
23/7
23/7
—
—
—
—
—
—
—
—
CNPUE6
CNPUE6
CNEN6
CNEN6
22/6
22/6
—
—
—
—
—
—
—
—
CNPUE21
CNPUE5
CNPUE5
CNEN21
CNEN5
CNEN5
21/5
21/5
—
—
—
—
—
—
CNPUE20
CNPUE4
CNPUE4
CNEN20
CNEN4
CNEN4
20/4
20/4
—
—
—
—
—
—
CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000
CNEN19
CNPUE3
CNPUE3
CNEN3
CNEN3
19/3
19/3
—
—
—
—
—
—
CNPUE18 CNPUE17 CNPUE16 0000
CNEN18
CNPUE2
CNEN18
CNPUE2
CNEN2
CNEN2
18/2
18/2
—
—
—
—
CNEN17
CNPUE1
CNEN17
CNPUE1
CNEN1
CNEN1
17/1
17/1
—
—
—
—
CNEN16
CNPUE0
CNEN16
CNPUE0
CNEN0
CNEN0
16/0
16/0
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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