LP2996M National Semiconductor, LP2996M Datasheet - Page 12
![IC, REG DDR TERMINATION, SMD, SO-8](/photos/18/98/189854/ge8so805-40_sml.jpg)
LP2996M
Manufacturer Part Number
LP2996M
Description
IC, REG DDR TERMINATION, SMD, SO-8
Manufacturer
National Semiconductor
Datasheet
1.LP2996M.pdf
(18 pages)
Specifications of LP2996M
Primary Input Voltage
2.5V
Output Voltage
1.35V
No. Of Pins
8
Output Current
1.5A
Voltage Regulator Case Style
SOIC
Operating Temperature Range
0°C To +125°C
Svhc
No SVHC (15-Dec-2010)
Output Voltage Fixed
1.35V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DDR-II APPLICATIONS
With the separate VDDQ pin and an internal resistor divider
it is possible to use the LP2996 in applications utilizing DDR-
II memory.
tions of recommended circuits with output curves displayed
in the Typical Performance Characteristics.
If it is not desirable to use the 1.8V rail it is possible to connect
the output stage to a 3.3V rail. Care should be taken to not
exceed the maximum junction temperature as the thermal
dissipation increases with lower V
Figure 6
and
Figure 7
FIGURE 7. SSTL-2 Implementation with higher voltage rails
TT
show several implementa-
FIGURE 9. DDR-II Termination with higher voltage rails
output voltages. For this
FIGURE 8. Recommended DDR-II Termination
Figure 6
shows
12
the recommended circuit configuration for DDR-II applica-
tions. The output stage is connected to the 1.8V rail and the
AVIN pin can be connected to either a 3.3V or 5V rail. For new
designs, the LP2997 or LP2998 is recommended for DDR-II
applications.
reason it is not recommended to power PVIN off a rail higher
than the nominal 3.3V. The advantage of this configuration is
that it has the ability to source and sink a higher maximum
continuous current.
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