ADP1755ACPZ-R7 Analog Devices Inc, ADP1755ACPZ-R7 Datasheet - Page 5

• Manufacturer Part Number: ADP1755ACPZ-R7
• Description: IC ADJ LDO REG 0.75V TO 3V 1.2A LFCSP-16
• Manufacturer: Analog Devices Inc

Specifications of ADP1755ACPZ-R7

• Primary Input Voltage: 3.6V
• Output Voltage Adjustable Range: 0.75V To 3V
• Dropout Voltage Vdo: 200mV
• No. Of Pins: 16
• Output Current: 1.2A
• Operating Temperature Range: -40°C To +125°C
• Package / Case: 16-LFCSP
• Mounting Type: Surface Mount
• Current - Output: 1.2A (Max)
• Voltage - Output: 0.75 ~ 3 V
• Voltage - Input: 1.6 ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Regulator Topology: Positive Adjustable
• Voltage - Dropout (typical): 0.105V @ 1.2A
• Number Of Regulators: 1
• Current - Limit (min): 1.5A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
SS to GND
PG to GND
SENSE/ADJ to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP1754/ADP1755 may be damaged if the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that T
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated. In applications with moderate power
dissipation and low PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits.
The junction temperature (T
ambient temperature (T
(P
package (θ
D
), and the junction-to-ambient thermal resistance of the
T
J
= T
JA
A
). T
+ (P
J
is calculated using the following formula:
D
× θ
JA
)
A
), the power dissipation of the device
J
) of the device is dependent on the
J
is within the specified
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Rev. B | Page 5 of 20
Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
on PCB material, layout, and environmental conditions. The
specified values of θ
board. Refer to JEDEC JESD51-7 for detailed information about
board construction. For more information, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
Ψ
with units of °C/W. Ψ
calculation using a 4-layer board. The JESD51-12 document,
Guidelines for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. Ψ
power flowing through multiple thermal paths rather than through
a single path as in thermal resistance, θ
paths include convection from the top of the package as well as
radiation from the package, factors that make Ψ
real-world applications. Maximum junction temperature (T
is calculated from the board temperature (T
dissipation (P
Refer to the JEDEC JESD51-8 and JESD51-12 documents for more
detailed information about Ψ
THERMAL RESISTANCE
θ
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
16-Lead LFCSP with Exposed Pad (CP-16-4)
ESD CAUTION
JA
JB
and Ψ
is the junction-to-board thermal characterization parameter
T
J
= T
JB
are specified for the worst-case conditions, that is, a
B
+ (P
D
) using the following formula:
D
× Ψ
JA
JB
JB
are based on a 4-layer, 4 in × 3 in circuit
)
of the package is based on modeling and
JB
.
ADP1754/ADP1755
JB
measures the component
JB
JA
. Therefore, Ψ
may vary, depending
JA
) of the package is
B
) and the power
θ
42
JA
JB
more useful in
Ψ
25.5
JB
JB
thermal
Unit
°C/W
J
)